| 1997 | Design and Performance Evaluation of a Cache Assist to implement Selective Caching. | Lizy Kurian John, Akila Subramanian |
| 1997 | Equivalence Checking Using Abstract BDDs. | Somesh Jha, Yuan Lu, Marius Minea, Edmund M. Clarke |
| 1997 | A Survey of Techniques for Formal Verification of Combinational Circuits. | Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli |
| 1997 | A New Processor Architecture for Digital Signal Transport Systems. | Minoru Inamori, Kenji Ishii, Akihiro Tsutsui, Kazuhiro Shirakawa, Hiroshi Nakada, Toshiaki Miyazaki |
| 1997 | A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. | Wei Hwang, Rajiv V. Joshi, Walter H. Henkels |
| 1997 | Integrated Diagnostics for Embedded Memory Built-in Self Test on Power PC | Craig Hunter |
| 1997 | Formal Verification of the HAL S1 System Cache Coherence Protocol. | Alan J. Hu, Masahiro Fujita, Chris Wilson |
| 1997 | An Integrated Placement and Synthesis Approach for Timing Closure of PowerPC Microprocessors. | Shervin Hojat, Paul Villarrubia |
| 1997 | High-Level Design Synthesis of a Low Power, VLIW Processor for the IS-54 VSELP Speech Encoder. | Russell E. Henning, Chaitali Chakrabarti |
| 1997 | Discrete Drive Selection for Continuous Sizing. | Ramsey W. Haddad, Lukas P. P. P. van Ginneken, Narendra V. Shenoy |
| 1997 | Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithms. | Sriram Govindarajan, Ranga Vemuri |
| 1997 | A Low Power Smart Vision System Based on Active Pixel Sensor Integrated with Programmable Neural Processor. | Wai-Chi Fang, Guang Yang, Bedabrata Pain, Bing J. Sheu |
| 1997 | Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. | Abhijit Dharchoudhury, David T. Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning |
| 1997 | An Evaluation of Asynchronous and Synchronous Design for Superscalar Architectures. | Andrew Davey, David Lloyd |
| 1997 | Divide & Conquer: A Strategy for Synthesis of Low Power Finite State Machines. | Aurobindo Dasgupta, Shantanu Ganguly |
| 1997 | A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits. | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero |
| 1997 | Time-Stamped Transition Density for the Estimation of Delay Dependent Switching Activities. | Hoon Choi, Seung Ho Hwang |
| 1997 | A Novel Test Set Design for Parametric Testing of Analog and Mixed-Signal Circuits. | Jin Chen, Akhileswaran Ramachandran |
| 1997 | Power Compiler: A Gate-Level Power Optimization and Synthesis System. | Benjamin Chen, Ivailo M. Nedelchev |
| 1997 | Design Optimization for High-speed Per-address Two-level Branch Predictors. | I-Cheng K. Chen, Chih-Chieh Lee, Matt Postiff, Trevor N. Mudge |
| 1997 | Instruction Prefetching Using Branch Prediction Information. | I-Cheng K. Chen, Chih-Chieh Lee, Trevor N. Mudge |
| 1997 | An Architectural Power Optimization Case Study using High-level Synthesis. | Chih-Tung Chen, Kayhan Kkakar |
| 1997 | Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits. | Fu-Chiung Cheng |
| 1997 | Design and Implementation of Low-Power Digit-Serial Multipliers. | Yun-Nan Chang, Janardhan H. Satyanarayana, Keshab K. Parhi |
| 1997 | Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect. | Norman Chang, Valery Kanevsky, O. Sam Nakagawa, Khalid Rahmat, Soo-Young Oh |