| 1997 | A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement. | John A. Chandy, Prithviraj Banerjee |
| 1997 | A Comparative Evaluation of Hierarchical Network Architecture of the HP-Convex Exemplar. | Robert Castaeda, Xiaodong Zhang, James M. Hoover Jr. |
| 1997 | Circuit-Based Description and Modeling of Electromagnetic Noise Effects in Packaged Low-Power Electronics. | Andreas C. Cangellaris, W. Pinello, Albert E. Ruehli |
| 1997 | Checking Formal Specifications under Simulation. | William Canfield, E. Allen Emerson, Avijit Saha |
| 1997 | PA-8000: A Case Study of Static and Dynamic Branch Prediction. | Carl Burch |
| 1997 | Practical Advances in Asynchronous Design. | Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun |
| 1997 | Novel Simulation of Deep-Submicron MOSFET Circuits. | Serban Bruma, Ralph H. J. M. Otten |
| 1997 | Formally Specifying and Mechanically Verifying Programs for the Motorola Complex Arithmetic Processor DSP. | Bishop Brock, Warren A. Hunt Jr. |
| 1997 | Enhanced Compression Techniques to Simplify Programm Decompression and Execution. | Maurcio Breternitz Jr., Roger Smith |
| 1997 | Asnchronous Wrapper for Heterogeneous Systems. | David S. Bormann, Peter Y. K. Cheung |
| 1997 | A TSC Evaluation Function for Combinational Circuits. | Cristiana Bolchini, Donatella Sciuto, Fabio Salice |
| 1997 | Properties of the Input Pattern Fault Model. | Ronald D. Blanton, John P. Hayes |
| 1997 | Formal Implementation Verification of the Bus Interface Unit for the Alpha 21264 Microprocessor. | Gabriel P. Bischoff, Karl S. Brace, Samir Jain, Rahul Razdan |
| 1997 | Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels. | M. Bacis, Giacomo Buonanno, Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto |
| 1997 | CMOS Gate Delay Models for General RLC Loading. | Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi |
| 1997 | Built-In Temperature Sensors for On-line Thermal Monitoring of Microelectronic Structures. | Karim Arabi, Bozena Kaminska |
| 1997 | Improving Design Turnaround Time via Two-Levels Hw/Sw Co-Simulation. | Alberto Allara, S. Filipponi, William Fornaciari, Fabio Salice, Donatella Sciuto |
| 1996 | A Design For Test Perspective on I/O Management. | Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer |
| 1996 | Pausible Clocking: A First Step Toward Heterogeneous Systems. | Kenneth Y. Yun, Ryan P. Donohue |
| 1996 | Clock-Delayed Domino for Adder and Combinational Logic Desig. | Gin Yee, Carl Sechen |
| 1996 | The Tempest approach to distributed shared memory. | David A. Wood, Mark D. Hill, James R. Larus |
| 1996 | On Design of Efficient Square Generator. | Chin-Long Wey |
| 1996 | A Better ATPG Algorithm and Its Design Principles. | Li-C. Wang, M. Ray Mercer, Thomas W. Williams |
| 1996 | On the Nature and Inadequacies of Transport Timing Delay Constructs in VHDL Descriptions. | Peter A. Walker, Sumit Ghosh |
| 1996 | Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath. | H. Fatih Ugurdag, Thomas E. Fuhrman |