| 1995 | Emulation verification of the Motorola 68060. | Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller |
| 1995 | A CMOS gate array with dynamic-termination GTL I/O circuits. | Junya Kudoh, Toshiro Takahashi, Yukio Umada, Masaharu Kimura, Shigeru Yamamoto, Youichi Ito |
| 1995 | A CMOS wave-pipelined image processor for real-time morphology . | Ram K. Krishnamurthy, Ramalingam Sridhar |
| 1995 | An enhanced algorithm for the minimization of exclusive-OR sum-of-products for incompletely specified functions. | Tomasz Kozlowski, Erik L. Dagless, Jonathan Saul |
| 1995 | High level profiling based low power synthesis technique. | Srinivas Katkoori, Nand Kumar, Ranga Vemuri |
| 1995 | Implicit state minimization of non-deterministic FSMs. | Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1995 | A dynamic cache sub-block design to reduce false sharing. | Murali Kadiyala, Laxmi N. Bhuyan |
| 1995 | SSM-MP: more scalability in shared-memory multi-processor. | Shigeaki Iwasa, Shung Ho Shing, Hisashi Mogi, Hiroshi Nozuwe, Hiroo Hayashi, Osamu Wakamori, Takashi Ohmizo, Kuninori Tanaka, Hiroshi Sakai, Mitsuo Saito |
| 1995 | Concurrent timing optimization of latch-based digital systems. | Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray |
| 1995 | A new architectural-level fault simulation using propagation prediction of grouped fault-effects. | Michael S. Hsiao, Janak H. Patel |
| 1995 | Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors. | Yatin Vasant Hoskote, Dinos Moundanos, Jacob A. Abraham |
| 1995 | EPNR: an energy-efficient automated layout synthesis package. | Glenn Holt, Akhilesh Tyagi |
| 1995 | An empirical study of datapath, memory hierarchy, and network in SIMD array architectures. | Martin C. Herbordt, Charles C. Weems |
| 1995 | Clock controller design in SuperSPARC II microprocessor. | Hong Hao, Kanti Bhabuthmal |
| 1995 | Implementing a STARI chip. | Mark R. Greenstreet |
| 1995 | Memory organization for video algorithms on programmable signal processors. | Eddy de Greef, Francky Catthoor, Hugo De Man |
| 1995 | Statistics on concurrent fault and design error simulation. | Brian Grayson, Saghir A. Shaikh, Stephen A. Szygenda |
| 1995 | Interrupt-based hardware support for profiling memory system performance. | Aaron Goldberg, John A. Trotter |
| 1995 | Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
| 1995 | Synthesis for testability of large complexity controllers. | Franco Fummi, Donatella Sciuto, M. Serro |
| 1995 | Adaptive routing in Clos networks. | Peter A. Franaszek, Christos J. Georgiou, Chung-Sheng Li |
| 1995 | Smart-pixel array processors based on optimal cellular neural networks for space sensor applications. | Wai-Chi Fang, Bing J. Sheu, Holger Venus, Rainer Sandau |
| 1995 | Efficient testability enhancement for combinational circuit. | Yu Fang, Alexander Albicki |
| 1995 | Systolic algorithms for tree pattern matching. | Abdel Ejnioui, N. Ranganathan |
| 1995 | VLSI issues in memory-system design for video signal processors. | Santanu Dutta, Wayne H. Wolf, Andrew Wolfe |