| 1994 | A Parallel CMOS 2's Complement Multiplier Based on 5: 3 Counter. | Z. Guan, P. Thomson, A. E. A. Almaini |
| 1994 | AS/400 PowerPC | Mike Gruver, Nghia Phan, Tony Aipperspach, Scott Hilker, Jerry Bartley |
| 1994 | Peephole Optimization of Asynchronous Macromodule Networks. | Ganesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand |
| 1994 | Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs. | Laurence Goodby, Alex Orailoglu, Paul M. Chau |
| 1994 | Fourier Transform based DS/FH Spread Spectrum Receiver. | Jack P. F. Glas, Sndor E. Skolnik |
| 1994 | A Parallel Method for Functional Verification of Medium and High Throughput DSP Synthesis. | Mark Genoe, Luc J. M. Claesen, Hugo De Man |
| 1994 | Analysis of Multiprocessor Memory Refernce Behavior. | Jeffrey D. Gee, Alan Jay Smith |
| 1994 | Thermal Design of an Advanced Multichip Module for a RISC Processor. | Atul Garg, T.-L. Sham, Hans J. Greub, James Loy, John F. McDonald |
| 1994 | Single Chip PCI Bridge and Memory Controller for PowerPC | Michael J. Garcia, Brian K. Reynolds |
| 1994 | The Design and Evaluation of an Asynchronous Microprocessor. | Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, Steve Temple, John V. Woods |
| 1994 | Simulating Uniform Lossy Lines by the Time-Domain Modal Analysis. | Ali El-Zein, Monjurul Haque, Salim Chowdhury |
| 1994 | Asymptotic Limits of Video Signal Processing Architectures. | Santanu Dutta, Wayne H. Wolf |
| 1994 | A Multi-Schedule Approach to High-Level Synthesis. | Mehmet Emin Dalkili, Vijay Pitchumani |
| 1994 | Two-phase Logic Design by Hardware Flowcharts. | Kevin Covey, Sandra Murdock, Thomas R. Shiple |
| 1994 | Write Buffer Design for On-Chip Cache. | Pong P. Chu, Ramana Gottipati |
| 1994 | A Self-Timed Divider Using RSD Number System. | Kiyoung Choi, KiJong Lee, Jun-Woo Kang |
| 1994 | A Structural Approach to State Space Decomposition for Approximate Reachability Analysis. | Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi |
| 1994 | On Retiming for FPGA Logic Module Minimization. | Yao-Ping Chen, D. F. Wong |
| 1994 | Latch Design for Transient Pulse Tolerance. | Hungse Cha, Janak H. Patel |
| 1994 | Architectural Verification of Processors Using Symbolic Instruction Graphs. | Ashok K. Chandra, Vijay S. Iyengar, R. V. Jawalekar, Michael P. Mullen, Indira Nair, Barry K. Rosen |
| 1994 | The Future of Programmable Logic and Its Impact on Digital System Design. | William S. Carter |
| 1994 | Efficient State Space Pruning in Symbolic Backward Traversal. | Gianpiero Cabodi, Paolo Camurati, Stefano Quer |
| 1994 | In the Driver's Seat of BooleDozer. | Daniel Brand, Robert F. Damiano, Lukas P. P. P. van Ginneken, Anthony D. Drumm |
| 1994 | AS/400 | John M. Borkenhagen, Glen H. Handlogten, John D. Irish, Sheldon B. Levenstein |
| 1994 | Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches. | Sandeep Bhatia, Niraj K. Jha |