| 1994 | OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms. | Bernd Becker, Rolf Drechsler |
| 1994 | Initialization Isuues in the Synthesis of Asynchronous Circuits. | Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan |
| 1994 | A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits. | Sanghyeon Baeg, William A. Rogers |
| 1994 | Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. | Adnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton |
| 1994 | PowerPC Visual Simulator: Peeking Under the Hood of the PowerPC Engine. | M. Armstead, Michael Cogswell, S. Halverson, T. Musta |
| 1994 | An Arbitration Tree Adapted to Object Oriented Associative Memories. | Denis Archambaud, Pascal Faudemay |
| 1994 | HW/SW Codesign for Embedded Telecom Systems. | Stefano Antoniazzi, Alessandro Balboni, William Fornaciari, Donatella Sciuto |
| 1994 | A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic. | Edwin de Angel, Earl E. Swartzlander Jr., Jacob A. Abraham |
| 1994 | On-Chip TEC-QED ECC for Ultra-Large, Single-Chip Memory Systems. | Fahad M. Alzahrani, Tom Chen |
| 1994 | Area & Time Limitations of FPGA-based Virtual Hardware. | Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke |
| 1994 | Distributed Reconfiguration of Fault Tolerant VLSI Mulipipeline Arrays with Constant Interstage Path Lengths. | Hussain Al-Asaad, Mankuan Michael Vai, James Feldman |
| 1994 | Emerging Techologies for Electronic Design and Test. | Prathima Agrawal |
| 1994 | Routing Architectures for Hierarchical Field Programmable Gate Arrays. | Aditya A. Aggarwal, David M. Lewis |
| 1993 | Neighbour State Transition Method for VLSI Optimization Problems. | Dian Zhou, F. Tsui |
| 1993 | An Intelligent I-Cache Prefetch Mechanism. | Honesty C. Young, Eugene J. Shekita |
| 1993 | Optimal Scheduling of Finite-State Machines. | Ti-Yen Yen, Wayne H. Wolf |
| 1993 | Fast Timing Analysis for Hardware-Software Co-Synthesis. | Wei Ye, Rolf Ernst, Thomas Benner, Jrg Henkel |
| 1993 | Bit-Splitting for Testability Enhancement in Scan-Based Design. | Xiaodong Xie, Alexander Albicki |
| 1993 | A New Modulo 2 | Artur Wrzyszcz, David Milford |
| 1993 | Pica: An Ultra-Light Processor for High-Througput Applications. | D. Scott Wills, W. Stephen Lacy, Huy Cat, Michael A. Hopper, Ashutosh Razdan, Sek M. Chai |
| 1993 | Design for Testability: Today and in the Future. | Thomas W. Williams |
| 1993 | Design Guidelines and Testability Assessment. | Brian R. Wilkins, C. Shi |
| 1993 | A New High Performance Field Programmable Gate Array Family. | Telle Whitney, Jeff Schlageter |
| 1993 | ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits. | Chin-Long Wey, Ming-Der Shieh, P. David Fisher |
| 1993 | A Memory Controller with an Integrated Graphics Processor. | John Watkins, Raymond Roth, Michael Hsieh, William Radke, Donald Hejna, Byung Kim, Richard Tom |