| 1993 | Determining Cost-Effective Multiple Issue Processor Designs. | Thomas M. Conte, William H. Mangione-Smith |
| 1993 | Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip. | Luc J. M. Claesen, Joan Daemen, Mark Genoe, G. Peeters |
| 1993 | A Partial Scan Cost Estimation Method at the System Level. | Scott Chiu, Christos A. Papachristou |
| 1993 | Trail: A Track-Based Logging Disk Architecture for Zero-Overhead Writes. | Tzi-cker Chiueh |
| 1993 | A Vector Memory System Based on Wafer-Scale Integrated Memory Arrays. | Tzi-cker Chiueh |
| 1993 | Hardware Verification Using Symbolic State Transition Graphs. | Pinhong Chen, Jyuo-Min Shyu, Liang-Gee Chen |
| 1993 | A Path Sensitization Approach to Area Reduction. | Hsi-Chuan Chen, Siu-Wing Cheng, Yaun-Chung Hsu, David Hung-Chang Du |
| 1993 | The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling Problem. | Samit Chaudhuri, Robert A. Walker, John Mitchell |
| 1993 | Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters. | Abhijit Chatterjee, Rabindra K. Roy |
| 1993 | A Logic-Level Model for alpha-Paricle Hits in CMOS Circuits. | Hungse Cha, Janak H. Patel |
| 1993 | Cluster-Oriented Scheduling in Pipelined Data Path Syntesis. | Ching-Tang Chang, Kenneth Rose, Robert A. Walker |
| 1993 | Evaluation of an Object-Caching Coprocessor Design for Object-Oriented Systems. | J. Morris Chang, Edward F. Gehringer |
| 1993 | Exploiting Cofactoring for Efficient FSM Symbolic Traversal Based on the Transition Relation. | Gianpiero Cabodi, Paolo Camurati |
| 1993 | The Spring Scheduling Co-Processor: A Scheduling Accelerator. | Wayne P. Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems |
| 1993 | Functional Fault Models and Gate Level Coverage for Sequential Architectures. | Giacomo Buonanno, Franco Fummi, Donatella Sciuto |
| 1993 | Symbolic Analysis Methods for Masks, Circuits, and Systems. | Randal E. Bryant |
| 1993 | The PowerPC 601 Design Methodology. | Timothy B. Brodnax, Mike Schiffli, Floyd Watson |
| 1993 | System Factorization in Codesign: A Case Study of the Use of Formal Techniques to Achieve Hardware-Software Decomposition. | Bhaskar Bose, M. Esen Tuna, Steven D. Johnson |
| 1993 | A Split Data Cache for Superscalar Processors. | Rodney Boleyn, James Debardelaben, Vivek Tiwari, Andrew Wolfe |
| 1993 | Fidelity and Near-Optimality of Elmore-Based Routing Constructions. | Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins |
| 1993 | Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan. | Sandeep Bhatia, Niraj K. Jha |
| 1993 | A Comparison of Synchronous and Asynchronous FSMD Designs. | Richard Auletta, Robert B. Reese, Cherrice Traver |
| 1993 | The Splash 2 Processor and Applications. | Jeffrey M. Arnold, Duncan A. Buell, Dzung T. Hoang, Daniel V. Pryor, Nabeel Shirazi, Mark R. Thistle |
| 1993 | Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine. | Hideki Ando, Chikako Nakanishi, Hirohisa Machida, Tetsuya Hara, Satoru Kishida, Masao Nakaya |
| 1993 | An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. | Tod Amon, Henrik Hulgaard, Steven M. Burns, Gaetano Borriello |