| 1989 | Scheduling unequal length tests in high performance VLSI system implementations. | John Y. Sayah, Charles R. Kime |
| 1989 | A channelless layout for multilevel synthesis with compiled cells. | Gabriele Saucier, Rgis Leveugle, Pierre Abouzeid |
| 1989 | Parallel-concurrent fault simulation. | Daniel G. Saab, Ibrahim N. Hajj, Joseph T. Rahmeh |
| 1989 | Computer aided design system for VLSI interconnections. | Jerzy W. Rozenblit, John L. Prince, Olgierd A. Palusinski, T. D. Whipple |
| 1989 | The bus interface and paging units of the i860TM microprocessor. | Michael W. Rhodehamel |
| 1989 | The matrix transform chip. | Sailesh K. Rao |
| 1989 | A design of a memory management unit for object-based systems. | Umakishore Ramachandran, M. Yousef Amin Khalidi |
| 1989 | DAGAR: an automatic pipelined microarchitecture synthesis system. | Vijay K. Raj |
| 1989 | Motion estimation VLSI architecture for image coding. | Gilles Privat, Marc Renaudin |
| 1989 | Accurate prediction of physical design characteristics for random logic. | Massoud Pedram, Bryan Preas |
| 1989 | Logic decomposition algorithms for the timing optimization of multi-level logic. | Pierre G. Paulin, Franck J. Poirot |
| 1989 | A test generation system for path delay faults. | Srinivas Patil, Sudhakar M. Reddy |
| 1989 | Architectural features of the i860(TM)-microprocessor RISC core and on-chip caches. | Piyush Patel, Diane Douglass |
| 1989 | A flexible architecture for neural networks. | J. Ouali, Gabriele Saucier |
| 1989 | A high performance BiCMOS 32-bit microprocessor. | Yasuhiro Nakatsuka, Takashi Hotta, Shigeya Tanaka, Tadaaki Bandoh, Ryuichi Satomura, Syuichi Nakagami, Tetsuo Nakano, Atsuo Hotta, Takashi Moriyama, Shigemi Adachi, Shoji Iwamoto |
| 1989 | Electromigration median time-to-failure based on a stochastic current waveform. | Farid N. Najm, Ibrahim N. Hajj, Ping Yang |
| 1989 | A logic network synthesis system, SYLON. | S. Muroga, X. Q. Xiang, J. Limqueco, L. P. Lin, K. C. Chen |
| 1989 | Adaptive and pipelined VLSI designs for tree-based codes. | Amar Mukherjee, N. Ranganathan, Mostafa A. Bassiouni |
| 1989 | Evolution in the application of ASICs in the second-generation Titan. | Glen S. Miranker, Jon Rubinstein, John Sanguinetti |
| 1989 | High performance circuits for the i486TM processor. | James Miller, Ben Roberts, Paul Madland |
| 1989 | A fast floor planning algorithm for architectural evaluation. | Michael C. McFarland |
| 1989 | Logic minimization for factored forms. | Abdul A. Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1989 | Circuit technologies for BiCMOS VLSI's as computer elements. | Hideo Maejima, Tadaaki Bandoh, Yoji Nishio, Tadashi Fukushima, Masanori Odaka, Atsuo Hotta |
| 1989 | A VLSI module for IEEE floating-point multiplication/division/square root. | Paul Y. Lu, Kevin Dawallu |
| 1989 | Formal verification of state-machines using higher-order logic. | Paul Loewenstein |