| 1990 | Compacting randomly generated test sets. | James H. Aylor, James P. Cohoon, E. L. Feldhousen, Barry W. Johnson |
| 1990 | Testability driven synthesis of interacting finite state machines. | Pranav Ashar, Srinivas Devadas, A. Richard Newton |
| 1990 | An edge based netlist extractor for IC layouts. | Sandeep Aranake, Anil Dikshit, A. Arun |
| 1990 | Design aids and test results for laser-programmable logic arrays. | David L. Allen, Richard Goldenberg |
| 1989 | Systolic implementation of neural networks. | Mohammad Zubair, B. B. Madan |
| 1989 | Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture. | Yervant Zorian, Najmi Jarwala |
| 1989 | Intelligent backtracking in test generation for combinational circuits. | W. B. Zeng, D. Z. Wei |
| 1989 | Automatic signal net-matching for VLSI layout design. | Xiao-Ming Xiong, Dan Green, John Hardin, Lawrence Riedel |
| 1989 | OPAM: an efficient output phase assignment for multilevel logic minimization. | Chin-Long Wey, Sin-Min Chang, Jing-Yang Jou |
| 1989 | Issues in the test of artificial neural networks. | Frank Warkowski, Jens Leenstra, Jos Nijhuis, Lambert Spaanenburg |
| 1989 | A novel message switch for highly parallel systems. | Shiwei Wang, Yarsun Hsu, C. J. Tan |
| 1989 | IBM RISC chip design methodology. | Paul Villarrubia, Gary Nusbaum, Robert Masleid, P. T. Patel |
| 1989 | Mind: a module binder for high level synthesis. | Chia-Jeng Tseng, Steven G. Rothweiler, Shailesh Sutarwala, Ajit M. Prabhu |
| 1989 | Counter-based residue arithmetic circuit for easily testable VLSI digital signal processing systems. | Nobuhiro Tomabechi |
| 1989 | High performance I/O processors for real-time pulse handling. | Masayoshi Tachibana, Yoshihisa Kondo, Yasuo Yamada, Masafumi Takahashi, Haruyuki Tago |
| 1989 | Automated synthesis of systems with interacting asynchronous (self-timed) and synchronous components. | P. A. Subrahmanyam |
| 1989 | An integrated floating point vector processor for DSP and scientific computing. | D. Spaderna, P. Green, K. Tam, T. Datta, M. Kumar |
| 1989 | FPC: a floating-point processor controller chip for systolic signal processing. | Ross A. W. Smith, Gerald E. Sobelman, George Luk, Koichi Suda, Jeff Bracken |
| 1989 | Generic ASIC architecture for digital signal processing. | Stewart G. Smith, Ralph W. Morgan, Julian G. Payne |
| 1989 | An enhanced high performance combinational fault simulator using two-way parallelism. | Steven P. Smith |
| 1989 | An 80 MFLOPS floating-point engine in the Intel i860(TM) processor. | Hon P. Sit, Monica Rosenrauch Nofal, Sunhyuk Kimn |
| 1989 | A cost function based optimization technique for scheduling in data path synthesis. | Hyunchul Shin, Nam Sung Woo |
| 1989 | A 32-bit microprocessor with high performance bit-map manipulation instructions. | Toru Shimizu, Shunichi Iwata, Yuichi Saito, Toyohiko Yoshida, Masahito Matsuo, Junichi Hinata, Kazunori Saito |
| 1989 | Fast MOS circuit simulation with a direct equation solver. | Y.-H. Shih, S. M. Kang |
| 1989 | Built-in test methodology for a full custom processor chip. | Ravinder S. Shergill, Pak-Ho Yeung, Patrick A. Tucci |