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IEEE International Conference on Computer Design

ICCD

C

CORE rank

CORE rank (raw)

C

Fields of research

Computer Systems Engineering

Papers indexed

3,768

1988–2025

Papers per year

1988128 peak2025

ICCD papers

3,768 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2016Luminescent solar concentrator-based photovoltaic reconfiguration for hybrid and plug-in electric vehicles.Caiwen Ding, Hongjia Li, Weiwei Zheng, Yanzhi Wang, Naehyuck Chang, Xue Lin
2016Dynamic converter reconfiguration for near-threshold non-volatile processors using in-door energy harvesting.Caiwen Ding, Hongjia Li, Jingtong Hu, Yongpan Liu, Yanzhi Wang
2016Enabling technologies for memory compression: Metadata, mapping, and prediction.Arjun Deb, Paolo Faraboschi, Ali Shafiee, Naveen Muralimanohar, Rajeev Balasubramonian, Robert Schreiber
2016Extending On-chip Interconnects for rack-level remote resource access.Yisong Chang, Ke Zhang, Sally A. McKee, Lixin Zhang, Mingyu Chen, Liqiang Ren, Zhiwei Xu
2016Speculative path power estimation using trace-driven simulations during high-level design phase.Saumya Chandra, Ramkumar Jayaseelan, Ravi Bhargava
2016BEOL stack-aware routability prediction from placement using data mining techniques.Wei-Ting Jonas Chan, Yang Du, Andrew B. Kahng, Siddhartha Nath, Kambiz Samadi
2016Concurrent Migration of Multiple Pages in software-managed hybrid main memory.Santiago Bock, Bruce R. Childers, Rami G. Melhem, Daniel Moss
2016Hardware-based attacks to compromise the cryptographic security of an election system.Mohammad-Mahdi Bidmeshki, Gaurav Rajavendra Reddy, Liwei Zhou, Jeyavijayan Rajendran, Yiorgos Makris
2016TESLA: Using microfluidics to thermally stabilize 3D stacked STT-RAM caches.Majed Valad Beigi, Gokhan Memik
2016Algorithms for CPU and DRAM DVFS under inefficiency constraints.Rizwana Begum, Mark Hempstead, Guru Prasad Srinivasa, Geoffrey Challen
2016Efficient mode changes in multi-mode systems.Akramul Azim, Sebastian Fischmeister
2016Dynamic single and Dual Rail spin transfer torque look up tables with enhanced robustness under CMOS and MTJ process variations.Aliyar Attaran, Hassan Salmani, Houman Homayoun, Hamid Mahmoodi
2016A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS.Samira Ataei, James E. Stine, Matthew R. Guthaus
2016Strategies for optimal operating point selection in timing speculative processors.Omid Assare, Rajesh K. Gupta
2016MASkIt: Soft error rate estimation for combinational circuits.Mart Anglada, Ramon Canal, Juan L. Aragn, Antonio Gonzlez
2016Chain-based pseudorandom tests for pre-silicon verification of CMP memory systems.Gabriel A. G. Andrade, Marleson Graf, Luiz C. V. dos Santos
201686 computer architecture simulators: A comparative study.Ayaz Akram, Lina Sawalha
2016Scalable memory fabric for silicon interposer-based multi-core systems.Itir Akgun, Jia Zhan, Yuangang Wang, Yuan Xie
2016A single-inductor-cascaded-stage topology for high conversion ratio boost regulator.Khondker Zakir Ahmed, Saibal Mukhopadhyay
2016Efficient processor allocation in a reconfigurable CMP architecture for dark silicon era.Fatemeh Aghaaliakbari, Mohaddeseh Hoveida, Mohammad Arjomand, Majid Jalili, Hamid Sarbazi-Azad
2016Exploring static and dynamic flash-based FPGA design topologies.Monther Abusultan, Sunil P. Khatri
2016Implementing low power digital circuits using flash devices.Monther Abusultan, Sunil P. Khatri
2016DLL: A dynamic latency-aware load-balancing strategy in 2.5D NoC architecture.Chen Li, Sheng Ma, Lu Wang, Zicong Wang, Xia Zhao, Yang Guo
2016Tolerating more hard errors in MLC PCMs using compression.Majid Jalili, Hamid Sarbazi-Azad
2015A testing platform for on-drone computation.Wang Zhou, Dhruv Nair, Oki Gunawan, Theodore G. van Kessel, Hendrik F. Hamann
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