| 2014 | Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration. | Jianxing Wang, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, Hai Li |
| 2014 | ProactiveDRAM: A DRAM-initiated retention management scheme. | Jue Wang, Xiangyu Dong, Yuan Xie |
| 2014 | Built-in self-test for interposer-based 2.5D ICs. | Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik |
| 2014 | An energy efficient column-major backend for FPGA SpMV accelerators. | Yaman Umuroglu, Magnus Jahre |
| 2014 | CoolBudget: Data center power budgeting with workload and cooling asymmetry awareness. | Ozan Tuncer, Kalyan Vaidyanathan, Kenny C. Gross, Ayse K. Coskun |
| 2014 | BarTLB: Barren page resistant TLB for managed runtime languages. | Xin Tong, Andreas Moshovos |
| 2014 | 3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time. | Ishan G. Thakkar, Sudeep Pasricha |
| 2014 | The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost. | Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu |
| 2014 | Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. | Andreas Steininger, Varadan Savulimedu Veeravalli, Dan Alexandrescu, Enrico Costenaro, Lorena Anghel |
| 2014 | Updates of the ITRS design cost and power models. | Gary Smith |
| 2014 | Timing characterization of clock buffers for clock tree synthesis. | Can Sitik, Scott Lerner, Baris Taskin |
| 2014 | Timing error masking by exploiting operand value locality in SIMD architecture. | Jaehyeong Sim, Jun-Seok Park, Seungwook Paek, Lee-Sup Kim |
| 2014 | Energy efficiency improvement of renamed trace cache through the reduction of dependent path length. | Ryota Shioya, Hideki Ando |
| 2014 | Low write-energy STT-MRAMs using FinFET-based access transistors. | Alireza Shafaei, Yanzhi Wang, Massoud Pedram |
| 2014 | Boolean circuit design using emerging tunneling devices. | Behnam Sedighi, Joseph J. Nahas, Michael T. Niemier, Xiaobo Sharon Hu |
| 2014 | Static thread mapping for NoCs via binary instrumentation traces. | Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead, Ankit More |
| 2014 | REEM: Failure/non-failure region estimation method for SRAM yield analysis. | Manish Rana, Ramon Canal |
| 2014 | Accurate prediction of detailed routing congestion using supervised data learning. | Zhongdong Qi, Yici Cai, Qiang Zhou |
| 2014 | Automated generation of battery aging models from datasheets. | Massimo Petricca, Donghwa Shin, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2014 | NVSleep: Using non-volatile memory to enable fast sleep/wakeup of idle cores. | Xiang Pan, Radu Teodorescu |
| 2014 | Optimal variable ordering in ZBDD-based path representations for directed acyclic graphs. | Stelios N. Neophytou, Maria K. Michael |
| 2014 | Software pipelining of dataflow programs with dynamic constructs on multi-core processor. | Yogesh Murarka, Pankaj Shailendra Gode, Sirish Kumar Pasupuleti, Soma Kohli |
| 2014 | Dynamic variability management in mobile multicore processors under lifetime constraints. | Pietro Mercati, Francesco Paterna, Andrea Bartolini, Luca Benini, Tajana Simunic Rosing |
| 2014 | HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs. | Yuchun Ma, Jinglan Liu, Chao Zhang, Wayne Luk |
| 2014 | SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache. | Pritam Majumder, T. Venkata Kalyan, Madhu Mutyam |