| 2012 | Memory module-level testing and error behaviors for phase change memory. | Zhe Zhang, Weijun Xiao, Nohhyun Park, David J. Lilja |
| 2012 | SOLE: Speculative one-cycle load execution with scalability, high-performance and energy-efficiency. | Zhen-Hao Zhang, Dong Tong, Xiaoyin Wang, Jiangfang Yi, Keyi Wang |
| 2012 | Fast error aware model for arithmetic and logic circuits. | Samy Zaynoun, Muhammed S. Khairy, Ahmed M. Eltawil, Fadi J. Kurdahi, Amin Khajeh |
| 2012 | Reinforcement learning based dynamic power management with a hybrid power supply. | Siyu Yue, Di Zhu, Yanzhi Wang, Massoud Pedram |
| 2012 | Row buffer locality aware caching policies for hybrid memories. | HanBin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael Harding, Onur Mutlu |
| 2012 | WaveSync: A low-latency source synchronous bypass network-on-chip architecture. | Yoon Seok Yang, Reeshav Kumar, Gwan Choi, Paul Gratz |
| 2012 | Post-layout OPE-predicted redundant wire insertion for clock skew minimization. | Jin-Tai Yan, Zhi-Wei Chen |
| 2012 | Hierarchical modeling of Phase Change memory for reliable design. | Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu Cao |
| 2012 | DuSCA: A multi-channeling strategy for doubling communication capacity in wireless NoC. | Yi Wang, Dan Zhao, Jian Li |
| 2012 | A 3D stacked high performance scalable architecture for 3D Fourier Transform. | George Razvan Voicu, Marius Enachescu, Sorin Dan Cotofana |
| 2012 | Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications. | Christos Vezyrtzis, Yannis P. Tsividis, Steven M. Nowick |
| 2012 | Analyzing the optimal ratio of SRAM banks in hybrid caches. | Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro Lpez, Jos Duato |
| 2012 | FlexRAM: Toward an advanced Intelligent Memory system: A retrospective paper. | Josep Torrellas |
| 2012 | Clock mesh synthesis method using the Earth Mover's Distance under transformations. | Ying Teng, Baris Taskin |
| 2012 | A novel profiled side-channel attack in presence of high Algorithmic Noise. | Mostafa M. I. Taha, Patrick Schaumont |
| 2012 | Parameterized free space redistribution for engineering change in placement of integrated circuits. | Taraneh Taghavi, Shyam Ramji, Frank Musante, Suhasini Rege |
| 2012 | Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening. | Subramanian Poothamkurissi Swaminathan, Pey-Chang Kent Lin, Sunil P. Khatri |
| 2012 | Oblivious routing design for mesh networks to achieve a new worst-case throughput bound. | Guang Sun, Chia-Wei Chang, Bill Lin, Lieguang Zeng |
| 2012 | Non-enumerative generation of statistical path delays for ATPG. | Ahish Mysore Somashekar, Spyros Tragoudas, Sreenivas Gangadhar, Rathish Jayabharathi |
| 2012 | Embedded way prediction for last-level caches. | Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch |
| 2012 | Multi-voltage domain clock mesh design. | Can Sitik, Baris Taskin |
| 2012 | Integration of correct-by-construction BIP models into the MetroII design space exploration flow. | Alena Simalatsar, Liangpeng Guo, Marius Bozga, Roberto Passerone |
| 2012 | Exploiting microarchitectural redundancy for defect tolerance. | Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger |
| 2012 | Power-sensitive multithreaded architecture. | John S. Seng, Dean M. Tullsen, George Z. N. Cai |
| 2012 | Retrospective on "Power-Sensitive Multithreaded Architecture". | John S. Seng, Dean M. Tullsen, George Z. N. Cai |