| 2011 | A machine learning approach to modeling power and performance of chip multiprocessors. | Changshu Zhang, Arun Ravindran, Kushal Datta, Arindam Mukherjee, Bharat Joshi |
| 2011 | Reduced complexity test generation algorithms for transition fault diagnosis. | Yu Zhang, Vishwani D. Agrawal |
| 2011 | Pre-assignment RDL routing via extraction of maximal net sequence. | Jin-Tai Yan, Zhi-Wei Chen |
| 2011 | Evaluation of issue queue delay: Banking tag RAM and identifying correct critical path. | Kyohei Yamaguchi, Yuya Kora, Hideki Ando |
| 2011 | FIMSIM: A fault injection infrastructure for microarchitectural simulators. | Gulay Yalcin, Osman S. Unsal, Adrin Cristal, Mateo Valero |
| 2011 | TAP prediction: Reusing conditional branch predictor for indirect branches with Target Address Pointers. | Zichao Xie, Dong Tong, Mingkai Huang, Xiaoyin Wang, Qinqing Shi, Xu Cheng |
| 2011 | Thread-aware dynamic shared cache compression in multi-core processors. | Yuejian Xie, Gabriel H. Loh |
| 2011 | Path aware event scheduler in HoldAdvisor for fixing min timing violations. | Tong Xiao, Harshinder Bagga, George J. Chen, Richard Cheung, Raghu Pattipati |
| 2011 | Distributed thermal management for embedded heterogeneous MPSoCs with dedicated hardware accelerators. | Yen-Kuan Wu, Shervin Sharifi, Tajana Simunic Rosing |
| 2011 | Sequential hardware Trojan: Side-channel aware design and placement. | Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Tatini Mal-Sarkar, Swarup Bhunia |
| 2011 | Energy-efficient multi-level cell phase-change memory system with data encoding. | Jue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie |
| 2011 | RoShaQ: High-performance on-chip router with shared queues. | Anh Thien Tran, Bevan M. Baas |
| 2011 | The DIMM tree architecture: A high bandwidth and scalable memory system. | Kanit Therdsteerasukdi, Gyungsu Byun, Jeremy Ir, Glenn Reinman, Jason Cong, M. Frank Chang |
| 2011 | ROA-brick topology for rotary resonant clocks. | Ying Teng, Jianchao Lu, Baris Taskin |
| 2011 | Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory. | Guangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie |
| 2011 | A study on relating redundancy removal in classical circuits to reversible mapping. | Sayeeda Sultana, Katarzyna Radecka, Yu Pang |
| 2011 | Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors. | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson |
| 2011 | A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer. | Wei Shi, Weixia Xu, Hongguang Ren, Qiang Dou, Zhiying Wang, Li Shen, Cong Liu |
| 2011 | Leveraging torus topology with deadlock recovery for cost-efficient on-chip network. | Minjeong Shin, John Kim |
| 2011 | A simple pipelined squaring circuit for DSP. | Vladimir Risojevic, Aleksej Avramovic, Zdenka Babic, Patricio Bulic |
| 2011 | Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection. | Justin Rilling, David Graziano, Jamin Hitchcock, Tim Meyer, Xinying Wang, Phillip H. Jones, Joseph Zambreno |
| 2011 | Hybrid system level power consumption estimation for FPGA-based MPSoC. | Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Smal Niar, Eric Senn, Jean-Luc Dekeyser |
| 2011 | Hardware Trojans: The defense and attack of integrated circuits. | Trey Reece, William H. Robinson |
| 2011 | CPACT - The conditional parameter adjustment cache tuner for dual-core architectures. | Marisha Rawlins, Ann Gordon-Ross |
| 2011 | Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technology. | Vikram G. Rao, Hamid Mahmoodi |