| 2011 | Blue team red team approach to hardware trust assessment. | Jeyavijayan Rajendran, Vinayaka Jyothi, Ramesh Karri |
| 2011 | Task model for on-chip communication infrastructure design for multicore systems. | Bharath Phanibhushana, Kunal P. Ganeshpure, Sandip Kundu |
| 2011 | Positive Davio-based synthesis algorithm for reversible logic. | Yu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka |
| 2011 | Low power, high throughput network-on-chip fabric for 3D multicore processors. | Vivek S. Nandakumar, Malgorzata Marek-Sadowska |
| 2011 | A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems. | Arslan Munir, Ann Gordon-Ross, Sanjay Ranka |
| 2011 | EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs. | Ankit More, Baris Taskin |
| 2011 | Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology. | Farshad Moradi, Georgios Panagopoulos, Georgios Karakonstantis, Dag T. Wisland, Hamid Mahmoodi, Jens Kargaard Madsen, Kaushik Roy |
| 2011 | DPPC: Dynamic power partitioning and capping in chip multiprocessors. | Kai Ma, Xiaorui Wang, Yefu Wang |
| 2011 | Enhanced symbolic simulation of a round-robin arbiter. | Yongjian Li, Naiju Zeng, William N. N. Hung, Xiaoyu Song |
| 2011 | Runtime adaptable concurrent error detection for linear digital systems. | Yu Liu, Kaijie Wu |
| 2011 | Memory coherence in the age of multicores. | Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Srinivas Devadas |
| 2011 | Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset. | Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi |
| 2011 | A novel cryptographic key exchange scheme using resistors. | Pey-Chang Kent Lin, Alex Ivanov, Bradley Johnson, Sunil P. Khatri |
| 2011 | Using stochastic computing to implement digital image processing algorithms. | Peng Li, David J. Lilja |
| 2011 | AIG rewriting using 5-input cuts. | Nan Li, Elena Dubrova |
| 2011 | Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores. | Dean L. Lewis, Shreepad Panth, Xin Zhao, Sung Kyu Lim, Hsien-Hsin S. Lee |
| 2011 | Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA. | Yuanwu Lei, Yong Dou, Li Shen, Jie Zhou, Song Guo |
| 2011 | An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems. | Hyung Gyu Lee, Seungcheol Baek, Chrysostomos Nicopoulos, Jongman Kim |
| 2011 | Memristor-based IMPLY logic design procedure. | Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman |
| 2011 | Using content-aware bitcells to reduce static energy dissipation. | Fahrettin Koc, Osman Seckin Simsek, Oguz Ergin |
| 2011 | ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores. | Omer Khan, Henry Hoffmann, Mieszko Lis, Farrukh Hijaz, Anant Agarwal, Srinivas Devadas |
| 2011 | The convergence of HPC and embedded systems in our heterogeneous computing future. | David R. Kaeli, David Akodes |
| 2011 | A memristor-based memory cell using ambipolar operation. | Pilin Junsangsri, Fabrizio Lombardi |
| 2011 | Simultaneous continual flow pipeline architecture. | Komal Jothi, Mageda Sharafeddine, Haitham Akkary |
| 2011 | Is single-scheme Trojan prevention sufficient? | Yier Jin, Yiorgos Makris |