| 2010 | Towards cool and reliable digital systems: RT level CED techniques with runtime adaptability. | Yu Liu, Kaijie Wu |
| 2010 | Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging. | Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita |
| 2010 | Incremental gate sizing for late process changes. | John Lee, Puneet Gupta |
| 2010 | SWIFT: A SWing-reduced interconnect for a Token-based Network-on-Chip in 90nm CMOS. | Tushar Krishna, Jacob Postman, Christopher Edmonds, Li-Shiuan Peh, Patrick Chiang |
| 2010 | Efficient MIMD architectures for high-performance ray tracing. | Daniel M. Kopta, Josef B. Spjut, Erik Brunvand, Al Davis |
| 2010 | Toward reliable SRAM-based device identification. | Joonsoo Kim, Joonsoo Lee, Jacob A. Abraham |
| 2010 | Sub-threshold charge recovery circuits. | Mehrdad Khatir, Hassan Ghasemzadeh Mohammadi, Alireza Ejlali |
| 2010 | Insertion policy selection using Decision Tree Analysis. | Samira Manabi Khan, Daniel A. Jimnez |
| 2010 | Feasibility study of dynamic Trusted Platform Module. | Arun K. Kanuparthi, Mohamed Zahran, Ramesh Karri |
| 2010 | Exploiting application-dependent ambient temperature for accurate architectural simulation. | Hyung Beom Jang, Jinhang Choi, Ikroh Yoon, Sung-Soo Lim, Seungwon Shin, Naehyuck Chang, Sung Woo Chung |
| 2010 | Efficient test response compaction for robust BIST using parity sequences. | Thomas Indlekofer, Michael Schnittger, Sybille Hellebrand |
| 2010 | Efficient provably good OPC modeling and its applications to interconnect optimization. | Shih-Lun Huang, Chung-Wei Lin, Yao-Wen Chang |
| 2010 | Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array. | Vinayak Honkote, Baris Taskin |
| 2010 | Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU. | Seokin Hong, Soontae Kim |
| 2010 | Threads vs. caches: Modeling the behavior of parallel workloads. | Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser |
| 2010 | Enhancing dual-Vt design with consideration of on-chip temperature variation. | Junjun Gu, Gang Qu, Lin Yuan |
| 2010 | VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture. | Vaibhav Gupta, Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy |
| 2010 | DDPSL: An easy way of defining properties. | Luigi Di Guglielmo, Franco Fummi, Nicola Orlandi, Graziano Pravadelli |
| 2010 | M5 based EDGE architecture modeling. | Pengfei Gou, Qingbo Li, Yinghan Jin, Qi Zheng, Bing Yang, Mingyan Yu, Jinxiang Wang |
| 2010 | A flexible simulation methodology and tool for nanoarray-based architectures. | Stefano Frache, Mariagrazia Graziano, Maurizio Zamboni |
| 2010 | Automotive embedded driver assistance: A real-time low-power FPGA stereo engine using semi-global matching. | Felix Eberli |
| 2010 | BDD-based circuit restructuring for reducing dynamic power. | Quang Dinh, Deming Chen, Martin D. F. Wong |
| 2010 | LMS-based low-complexity game workload prediction for DVFS. | Benedikt Dietrich, Swaroop Nunna, Dip Goswami, Samarjit Chakraborty, Matthias Gries |
| 2010 | A study on performance benefits of core morphing in an asymmetric multicore processor. | Anup Das, Rance Rodrigues, Israel Koren, Sandip Kundu |
| 2010 | Thermal-aware scratchpad memory design and allocation. | Morteza Damavandpeyma, Sander Stuijk, Twan Basten, Marc Geilen, Henk Corporaal |