| 2010 | Helia: Heterogeneous Interconnect for Low Resolution Cache Access in snoop-based chip multiprocessors. | Ali Shafiee, Narges Shahidi, Amirali Baniasadi |
| 2010 | Welcome to ICCD 2010! | Peter-Michael Seidel, Georgi Gaydadjiev, Sofine Tahar, Lars J. Svensson |
| 2010 | A voting-based working set assessment scheme for dynamic cache resizing mechanisms. | Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi |
| 2010 | The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms. | Glauco Borges Valim dos Santos, Tiago Reimann, Marcelo O. Johann, Ricardo Reis |
| 2010 | Elaboration-time synthesis of high-level language constructs in SystemC-based microarchitectural simulators. | Zhuo Ruan, Kurtis Cahill, David A. Penry |
| 2010 | Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimization. | Sanghamitra Roy, Koushik Chakraborty |
| 2010 | IP characterization methodology for fast and accurate power consumption estimation at transactional level model. | Michel Rogers-Valle, Marc-Andr Cantin, Laurent Moss, Guy Bois |
| 2010 | A high performance router with dynamic buffer allocation for on-chip interconnect networks. | Shubo Qi, Minxuan Zhang, Jinwen Li, Tianlei Zhao, Chengyi Zhang, Shaoqing Li |
| 2010 | Temperature-to-power mapping. | Zhenyu Qi, Brett H. Meyer, Wei Huang, Robert J. Ribando, Kevin Skadron, Mircea R. Stan |
| 2010 | QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin. | Yue Qian, Zhonghai Lu, Qiang Dou |
| 2010 | Predicting the throughput of multiprocessor applications under dynamic workload. | Peter Poplavko, Marc Geilen, Twan Basten |
| 2010 | An energy model for graphics processing units. | Jeff Pool, Anselmo Lastra, Montek Singh |
| 2010 | Computational models for the age of multicore processing. | Wolfgang J. Paul |
| 2010 | Crosstalk modeling to predict channel delay in Network-on-Chips. | Ahmad Patooghy, Seyed Ghassem Miremadi, Mansour Shafaei |
| 2010 | Spintronic logic gates for spintronic data using magnetic tunnel junctions. | Shruti Patil, Andrew Lyle, Jonathan D. Harms, David J. Lilja, Jianping Wang |
| 2010 | Dynamic register file partitioning in superscalar microprocessors for energy efficiency. | Meltem Ozsoy, Yusuf Onur Koberber, Mehmet Kayaalp, Oguz Ergin |
| 2010 | Rate-monotonic scheduling for reducing system-wide energy consumption for hard real-time systems. | Linwei Niu |
| 2010 | High throughput, low set-up time, reconfigurable linear Feedback Shift Registers. | Rick J. M. Nas, C. H. van Berkel |
| 2010 | RTOS-aware modeling of embedded hardware/software systems. | Matthias Mller, Joachim Gerlach, Wolfgang Rosenstiel |
| 2010 | Energy optimal on-line Self-Test of microprocessors in WSN nodes. | Andreas Merentitis, Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis |
| 2010 | Inter-socket victim cacheing for platform power reduction. | Subhra Mazumdar, Dean M. Tullsen, Justin J. Song |
| 2010 | Boolean factoring with multi-objective goals. | Mayler G. A. Martins, Leomar S. da Rosa Jr., Anders B. Rasmussen, Renato P. Ribas, Andr Incio Reis |
| 2010 | Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms. | Shohreh Sharif Mansouri, Elena Dubrova |
| 2010 | A co-processor approach for accelerating data-structure intensive algorithms. | Jason Loew, Jesse Elwell, Dmitry Ponomarev, Patrick H. Madden |
| 2010 | DfT optimization for pre-bond testing of 3D-SICs containing TSVs. | Jia Li, Dong Xiang |