| 2008 | Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs. | Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Lichun Bao |
| 2008 | A novel, highly SEU tolerant digital circuit design approach. | Rajesh Garg, Sunil P. Khatri |
| 2008 | Acceleration of a 3D target tracking algorithm using an application specific instruction set processor. | Sebastien Fontaine, Sylvain Goyette, J. M. Pierre Langlois, Guy Bois |
| 2008 | A parallel Steiner tree heuristic for macro cell routing. | Christian Fobel, Gary Grwal |
| 2008 | An improved micro-architecture for function approximation using piecewise quadratic interpolation. | Shai Erez, Guy Even |
| 2008 | Fine-grained parallel application specific computing for RNA secondary structure prediction on FPGA. | Yong Dou, Fei Xia, Xingming Zhou, Xuejun Yang |
| 2008 | Power switch characterization for fine-grained dynamic voltage scaling. | Liang Di, Mateja Putic, John C. Lach, Benton H. Calhoun |
| 2008 | Fast arbiters for on-chip network switches. | Giorgos Dimitrakopoulos, Nikos Chrysos, Costas Galanopoulos |
| 2008 | Post-silicon verification for cache coherence. | Andrew DeOrio, Adam Bauserman, Valeria Bertacco |
| 2008 | Application Specific Instruction set processor specialized for block motion estimation. | Marc-Andr Daigneault, J. M. Pierre Langlois, Jean-Pierre David |
| 2008 | Contention-aware application mapping for Network-on-Chip communication architectures. | Chen-Ling Chou, Radu Marculescu |
| 2008 | Test cost minimization through adaptive test development. | Mingjing Chen, Alex Orailoglu |
| 2008 | Ant Colony Optimization directed program abstraction for software bounded model checking. | Xueqi Cheng, Michael S. Hsiao |
| 2008 | Issue system protection mechanisms. | Pedro Chaparro, Jaume Abella, Javier Carretero, Xavier Vera |
| 2008 | Characterization of granularity and redundancy for SRAMs for optimal yield-per-area. | Jae Chul Cha, Sandeep K. Gupta |
| 2008 | A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions. | Dimitrios Bountas, Georgios I. Stamoulis, Nestoras E. Evmorfopoulos |
| 2008 | Analysis and minimization of practical energy in 45nm subthreshold logic circuits. | David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat |
| 2008 | Early stage FPGA interconnect leakage power estimation. | Shilpa Bhoj, Dinesh Bhatia |
| 2008 | Dynamically reconfigurable soft output MIMO detector. | Pankaj Bhagawat, Rajballav Dash, Gwan Choi |
| 2008 | Propositional approximations for bounded model checking of partial circuit designs. | Bernd Becker, Marc Herbstritt, Natalia Kalinnik, Matthew Lewis, Juri Lichtner, Tobias Nopper, Ralf Wimmer |
| 2008 | Applying speculation techniques to implement functional units. | Alberto A. Del Barrio, Mara C. Molina, Jose Manuel Mendias, Esther Andres Perez, Romn Hermida, Francisco Tirado |
| 2008 | Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. | Aditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang |
| 2008 | Improving SAT-based Combinational Equivalence Checking through circuit preprocessing. | Fabrcio Vivas Andrade, Leandro Maia Silva, Antnio Otvio Fernandes |
| 2008 | Ring data location prediction scheme for Non-Uniform Cache Architectures. | Sayaka Akioka, Feihui Li, Konrad Malkowski, Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin |
| 2008 | Characterization and design of sequential circuit elements to combat soft error. | Hamed Abrishami, Safar Hatami, Massoud Pedram |