| 2006 | Addressing Multicore Communication Challenges Using NoC Technology. | Drew Wingard |
| 2006 | Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. | Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja |
| 2006 | Simulation-based functional test justification using a decision-digram-based Boolean data miner. | Charles H.-P. Wen, Onur Guzey, Li-C. Wang |
| 2006 | Scale in Chip Interconnect requires Network Technology . | Enno Wein |
| 2006 | Improving Power and Data Efficiency with Threaded Memory Modules. | Frederick A. Ware, Craig Hampel |
| 2006 | System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors. | Xiaofang Wang, Sotirios G. Ziavras |
| 2006 | Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft Indexing. | Shuo Wang, Lei Wang |
| 2006 | Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection. | Jin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, Saurabh Bagchi |
| 2006 | An Efficient, Scalable Hardware Engine for Boolean SATisfiability. | Mandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi |
| 2006 | A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals. | Kimiyoshi Usami, Naoaki Ohkubo |
| 2006 | Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction. | Rasit Onur Topaloglu, Andrew B. Kahng |
| 2006 | Design Methodology of Regular Logic Bricks for Robust Integrated Circuits. | Kim Yaw Tong, Lawrence T. Pileggi |
| 2006 | Polaris: A System-Level Roadmap for On-Chip Interconnection Networks. | Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh |
| 2006 | Architectural Support for Run-Time Validation of Control Flow Transfer. | Yixin Shi, Sean Dempsey, Gyungho Lee |
| 2006 | A theory of Error-Rate Testing. | Shideh Shahidi, Sandeep K. Gupta |
| 2006 | Design and Implementation of the TRIPS Primary Memory System. | Simha Sethumadhavan, Robert G. McDonald, Rajagopalan Desikan, Doug Burger, Stephen W. Keckler |
| 2006 | Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache. | Nathan Sadler, Daniel J. Sorin |
| 2006 | An accurate Energy estimation framework for VLIW Processor Cores. | Sourav Roy, Rajat Bhatia, Ashish Mathur |
| 2006 | Assertion-Based Microarchitecture Design for Improved Reliability. | Vimal K. Reddy, Eric Rotenberg, Ahmed S. Al-Zawawi |
| 2006 | Customizable Fault Tolerant Caches for Embedded Processors. | Subramanian Ramaswamy, Sudhakar Yalamanchili |
| 2006 | A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips. | Dara Rahmati, Abbas Eslami Kiasari, Shaahin Hessabi, Hamid Sarbazi-Azad |
| 2006 | Power Droop Testing. | Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker |
| 2006 | An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks. | Sanjay Pant, David T. Blaauw |
| 2006 | Reduction of Crosstalk Pessimism using Tendency Graph Approach. | Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier |
| 2006 | A New Class of Sequential Circuits with Acyclic Test Generation Complexity. | Chia Yee Ooi, Hideo Fujiwara |