| 2006 | Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects. | Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye |
| 2006 | Reconfigurable CAM Architecture for Network Search Engines. | Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara |
| 2006 | Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy. | Dan Nicolaescu, Babak Salamat, Alexander V. Veidenbaum |
| 2006 | Patching Processor Design Errors. | Satish Narayanasamy, Bruce Carneal, Brad Calder |
| 2006 | Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture. | Tinoosh Mohsenin, Bevan M. Baas |
| 2006 | Delay and Area Efficient First-level Cache Soft Error Detection and Correction. | Karl Mohr, Lawrence Clark |
| 2006 | Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates. | Saraju P. Mohanty, Elias Kougianos |
| 2006 | Dynamic Co-Processor Architecture for Software Acceleration on CSoCs. | Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A. Najjar |
| 2006 | FPGA Implementation of High Speed FIR Filters Using Add and Shift Method. | Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner |
| 2006 | Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation. | Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan |
| 2006 | CMOS Comparators for High-Speed and Low-Power Applications. | Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri |
| 2006 | Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread Execution. | Yi Ma, Huiyang Zhou |
| 2006 | Microarchitecture and Performance Analysis of Godson-2 SMT Processor. | Zusong Li, Xianchao Xu, Weiwu Hu, Zhimin Tang |
| 2006 | Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses. | Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra |
| 2006 | Task Merging for Dynamic Power Management of Cyclic Applications in Real-Time Multi-Processor Systems. | Shaobo Liu, Qinru Qiu, Qing Wu |
| 2006 | Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors. | Sean Leventhal, Manoj Franklin |
| 2006 | RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. | Ho Fai Ko, Nicola Nicolici |
| 2006 | Iterative-Constructive Standard Cell Placer for High Speed and Low Power. | Sungjae Kim, Eugene Shragowitz |
| 2006 | Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI. | Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy |
| 2006 | Seqver : A Sequential Equivalence Verifier for Hardware Designs . | Daher Kaiss, Silvian Goldenberg, Zurab Khasidashvili |
| 2006 | Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach. | Hwisung Jung, Massoud Pedram |
| 2006 | Reduce Register Files Leakage Through Discharging Cells. | Lingling Jin, Wei Wu, Jun Yang, Chuanjun Zhang, Youtao Zhang |
| 2006 | Power/ground supply network optimization for power-gating. | Hailin Jiang, Malgorzata Marek-Sadowska |
| 2006 | Power-Constrained SOC Test Schedules through Utilization of Functional Buses. | Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara |
| 2006 | High-Level vs. RTL Combinational Equivalence: An Introduction. | Alan Hu |