| 2006 | Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling. | Kuo-Su Hsiao, Chung-Ho Chen |
| 2006 | RasP: An Area-efficient, On-chip Network. | Simon Hollis, Simon W. Moore |
| 2006 | Implementation and Evaluation of On-Chip Network Architectures. | Paul Gratz, Changkyu Kim, Robert G. McDonald, Stephen W. Keckler, Doug Burger |
| 2006 | An Enhancement for a Scheduling Logic Pipelined over two Cycles . | Ruben Gran Tejero, Enric Morancho, ngel Oliv, Jos Mara Llabera |
| 2006 | Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths . | Bita Gorjiara, Mehrdad Reshadi, Daniel Gajski |
| 2006 | On the Improvement of Statistical Static Timing Analysis. | Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri |
| 2006 | Long-term Performance Bottleneck Analysis and Prediction. | Fei Gao, Suleyman Sair |
| 2006 | A Pattern Generation Technique for Maximizing Power Supply Currents. | Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu |
| 2006 | Requirements and Concepts for Transaction Level Assertions. | Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, Michael Velten |
| 2006 | Partial Functional Manipulation Based Wirelength Minimization. | Avijit Dutta, David Z. Pan |
| 2006 | FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. | Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack |
| 2006 | Computer Architecture in the Many-Core Era. | William J. Dally |
| 2006 | Interconnect Considerations For High Performance Network on Chip Designs. | Uri Cummings |
| 2006 | Design and Implementation of Software Objects in Hardware. | Fu-Chiung Cheng, Hung-Chi Wu |
| 2006 | Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation Technique. | Kameshwar Chandrasekar, Michael S. Hsiao |
| 2006 | Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD. | Krishnendu Chakrabarty |
| 2006 | Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. | Marc Boule, Jean-Samuel Chenard, Zeljko Zilic |
| 2006 | Clustering-Based Microcode Compression. | Edson Borin, Maurcio Breternitz Jr., Youfeng Wu, Guido Araujo |
| 2006 | Scalable Sequential Equivalence Checking across Arbitrary Design Transformations . | Jason Baumgartner, Hari Mony, Viresh Paruthi, Robert Kanzelman, Geert Janssen |
| 2006 | Trends and Future Directions in Nano Structure Based Computing and Fabrication. | R. Iris Bahar |
| 2006 | Reliability Support for On-Chip Memories Using Networks-on-Chip. | Federico Angiolini, David Atienza, Srinivasan Murali, Luca Benini, Giovanni De Micheli |
| 2006 | Scaling Manufacturability Software to Thousands of Processors. | Fabio Angelillis |
| 2006 | FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems. | Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi |
| 2006 | Guiding Architectural SRAM Models. | Banit Agrawal, Timothy Sherwood |
| 2006 | Efficient Testing of RF MIMO Transceivers Used in WLAN Applications. | Erkan Acar, Sule Ozev |