| 2005 | ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values. | Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng |
| 2005 | Automatic Synthesis of Composable Sequential Quantum Boolean Circuits. | Li-Kai Chang, Fu-Chiung Cheng |
| 2005 | State Set Management for SAT-based Unbounded Model Checking. | Kameshwar Chandrasekar, Michael S. Hsiao |
| 2005 | Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism.. | Fernando Castro, Daniel Chaver, Luis Piuel, Manuel Prieto, Francisco Tirado, Michael C. Huang |
| 2005 | Incorporating Ef.cient Assertion Checkers into Hardware Emulation. | Marc Boule, Zeljko Zilic |
| 2005 | Memory Bank Predictors. | Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio Gonzlez |
| 2005 | Towards the Formal Verification of Lower System Layers in Automotive Systems. | Sven Beyer, Peter Bhm, Michael Gerke, Mark A. Hillebrand, Thomas In der Rieden, Steffen Knapp, Dirk Leinenbach, Wolfgang J. Paul |
| 2005 | Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. | Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy |
| 2005 | FRAM Memory Technology - Advantages for Low Power, Fast Write, High Endurance Applications. | Rick Bailey, Glen Fox, Jarrod Eliason, Marty Depner, Daesig Kim, Edwin Jabillo, John Groat, John Walbert, Scott R. Summerfelt, K. R. Udayakumar, John Rodriquez, Keith Remack, K. Boku, John Gertas |
| 2005 | Challenges in the Formal Verification of Complete State-of-the-Art Processors. | Nathaniel Ayewah, Nikhil Kikkeri, Peter-Michael Seidel |
| 2005 | Deployment of Better Than Worst-Case Design: Solutions and Needs. | Todd M. Austin, Valeria Bertacco |
| 2005 | A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. | Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De |
| 2005 | X-Routing using Two Manhattan Route Instances. | Seraj Ahmad, Nikhil Jayakumar, Vijay Balasubramanian, Edward Hursey, Sunil P. Khatri, Rabi N. Mahapatra |
| 2005 | Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. | Anuradha Agarwal, Ranga Vemuri |
| 2005 | Near-memory Caching for Improved Energy Consumption. | Nevine AbouGhazaleh, Bruce R. Childers, Daniel Moss, Rami G. Melhem |
| 2005 | VGTA: Variation Aware Gate Timing Analysis. | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
| 2004 | A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. | Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan |
| 2004 | ACG-Adjacent Constraint Graph for General Floorplans. | Hai Zhou, Jia Wang |
| 2004 | Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. | Tianpei Zhang, Sachin S. Sapatnekar |
| 2004 | Cache Array Architecture Optimization at Deep Submicron Technologies. | Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann |
| 2004 | Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements using SystemC. | Jinwen Xi, Peixin Zhong |
| 2004 | In-System FPGA Prototyping of an Itanium Microarchitecture. | Roland E. Wunderlich, James C. Hoe |
| 2004 | Placement with Alignment and Performance Constraints Using the B*-Tree Representation. | Meng-Chen Wu, Yao-Wen Chang |
| 2004 | Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers. | Martin D. F. Wong |
| 2004 | Diagnosis of Hold Time Defects. | Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski |