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IEEE International Conference on Computer Design

ICCD

C

CORE rank

CORE rank (raw)

C

Fields of research

Computer Systems Engineering

Papers indexed

3,768

1988–2025

Papers per year

1988128 peak2025

ICCD papers

3,768 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2000Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies.Bong-Il Park, Hoon Choi, In-Cheol Park, Chong-Min Kyung
2000Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation.Song-Ra Pan, Yao-Wen Chang
2000Reducing Cost and Tolerating Defects in Page-based Intelligent Memory.Mark Oskin, Diana Keen, Justin Hensley, Lucian Vlad Lita, Frederic T. Chong
2000Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis.Koji Ohashi, Mineo Kaneko, Satoshi Tayu
2000Buffer Library Selection.Jos Luis Neves, Stephen T. Quay
2000Dynamic Flip-Flop with Improved Power.Nikola Nedovic, Vojin G. Oklobdzija
2000A Trace Based Evaluation of Speculative Branch Decoupling.Anshuman S. Nadkarni, Akhilesh Tyagi
2000A Power Perspective of Value Speculation for Superscalar Microprocessors.Rafael A. Moreno, Luis Piuel, Silvia Del Pino, Francisco Tirado
2000Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems.Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson
2000Output Prediction Logic: A High-Performance CMOS Design Technique.Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen
2000An Efficient and Accurate Model for RF/Microwave Spiral Inductors Using Microstrip Lines Theory.Nasser Masoumi, Safieddin Safavi-Naeini, Mohamed I. Elmasry
2000The M·COREAfzal Malik, Bill Moyer, Dan Cermak
2000Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures.Rafael Maestre, Milagros Fernndez, Romn Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh
2000Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing.I-Min Liu, Adnan Aziz
2000Minimization of Ordered Pseudo Kronecker Decision Diagrams.Per Lindgren, Rolf Drechsler, Bernd Becker
2000A Decompression Architecture for Low Power Embedded Systems.Haris Lekatsas, Jrg Henkel, Wayne H. Wolf
2000A Selective Temporal and Aggressive Spatial Cache System Based on Time Interval.Jung-Hoon Lee, Jang-Soo Lee, Shin-Dug Kim
2000OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet.Hemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha P. Chandrakasan
2000Efficient Logic Optimization Using Regularity Extraction.Thomas Kutzschebauch
2000Predictive Strategies for Low-Power RTOS Scheduling.Pavan Kumar, Mani B. Srivastava
2000Processors for Mobile Applications.Farinaz Koushanfar, Miodrag Potkonjak, Vandana Prabhu, Jan M. Rabaey
2000SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing.Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, Taisuke Boku
2000On Solving Stack-Based Incremental Satisfiability Problems.Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah
2000High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology.Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang
2000An Advanced Instruction Folding Mechanism for a Stackless Java Processor.Austin Kim, J. Morris Chang
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