| 2000 | An Adder Using Charge Sharing and its Application in DRAMs. | Hak-soo Yu, Songjun Lee, Jacob A. Abraham |
| 2000 | DRAM-Page Based Prediction and Prefetching. | Haifeng Yu, Gershon Kedem |
| 2000 | Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors. | Yanhong Yuan, Prithviraj Banerjee |
| 2000 | An Evaluation of Move-Based Multi-Way Partitioning Algorithms. | Elie Yarack, Joan Carletta |
| 2000 | Fast Subword Permutation Instructions Using Omega and Flip Network Stages. | Xiao Yang, Ruby B. Lee |
| 2000 | Worst Delay Estimation in Crosstalk Aware Static Timing Analysis. | Tong Xiao, Malgorzata Marek-Sadowska |
| 2000 | Rectilinear Block Placement Using B*-Trees. | Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang |
| 2000 | Source-Level Transformations for Improved Formal Verification. | Brian D. Winters, Alan J. Hu |
| 2000 | A Direct Mapping FPGA Architecture for Industrial Process Control Applications. | John T. Welch, Joan Carletta |
| 2000 | Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures. | Deependra Talla, Lizy Kurian John, Viktor S. Lapinskii, Brian L. Evans |
| 2000 | Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. | Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar |
| 2000 | High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. | Naran Sirisantana, Liqiong Wei, Kaushik Roy |
| 2000 | Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. | Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 2000 | Power-Sensitive Multithreaded Architecture. | John S. Seng, Dean M. Tullsen, George Z. N. Cai |
| 2000 | Analysis of Shared Memory Misses and Reference Patterns. | Jeffrey B. Rothman, Alan Jay Smith |
| 2000 | A Technique for Identifying RTL and Gate-Level Correspondences. | Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana |
| 2000 | Fast Hierarchical Floorplanning with Congestion and Timing Control. | Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh |
| 2000 | Interfacing Hardware and Software Using C++ Class Libraries. | Dinesh Ramanathan, Rajesh K. Gupta, Raymond Roth |
| 2000 | On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs. | Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation. | Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | On Multiple Precision Based Montgomery Multiplication without Precomputation of N0´ = -N0-1 mod W. | Hagen Ploog, Dirk Timmermann |
| 2000 | Hierarchical Simulation of a Multiprocessor Architecture. | Marius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra |
| 2000 | Symbolic Binding for Clustered VLIW ASIPs. | Satish Pillai, Margarida F. Jacome |
| 2000 | The Future of Populist Parallelism. | Gregory F. Pfister |
| 2000 | Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation. | Viresh Paruthi, Andreas Kuehlmann |