| 2001 | Performance Driven Global Routing Through Gradual Refinement. | Jiang Hu, Sachin S. Sapatnekar |
| 2001 | BDD Variable Ordering by Scatter Search. | William N. N. Hung, Xiaoyu Song |
| 2001 | An Analytical Model for Trace Cache Instruction Fetch Performance. | Afzal Hossain, Daniel J. Pease |
| 2001 | Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective. | Payam Heydari, Massoud Pedram |
| 2001 | Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits. | Payam Heydari, Massoud Pedram |
| 2001 | Efficient Function Approximation for Embedded and ASIC Applications. | James W. Hauser, Carla Neaderhouser Purdy |
| 2001 | Minimal Subset Evaluation: Rapid Warm-Up for Simulated Hardware State. | John W. Haskins Jr., Kevin Skadron |
| 2001 | Moore's Law Meets Shannon's Law: The Evolution of the Communication's Industry. | Lee M. Harrison |
| 2001 | Static Energy Reduction Techniques for Microprocessor Caches. | Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger |
| 2001 | RC-in RC-out Model Order Reduction Accurate up to Second Order Moments. | Pradeepsunder Ganesh, Charlie Chung-Ping Chen |
| 2001 | Performance Impact of Addressing Modes on Encryption Algorithms. | A. Murat Fiskiran, Ruby B. Lee |
| 2001 | A New Functional Test Program Generation Methodology. | Farzan Fallah, Koichiro Takayama |
| 2001 | A Low-Power Cache Design for CalmRISC | Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woong Jeong |
| 2001 | Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model. | Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang |
| 2001 | Efficient Systematic Error-correcting Codes for Semi-Delay-Insensitive Data Transmission. | Fu-Chiung Cheng, Shuen-Long Ho |
| 2001 | towards A formal Model of Shared Memory Consistency for Intel Itanium | Prosenjit Chatterjee, Ganesh Gopalakrishnan |
| 2001 | Fast Specification of Cycle-accurate Processor Models. | Felix Sheng-Ho Chang, Alan J. Hu |
| 2001 | Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages. | Noureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria |
| 2001 | Interconnect-centric Array Architectures for Minimum SRAM Access Time. | Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl |
| 2001 | Design Alternatives for Parallel Saturating Multioperand Adders. | Pablo I. Balzola, Michael J. Schulte, Jie Ruan, C. John Glossner, Erdem Hokenek |
| 2001 | Linear Time Hierarchical Capacitance Extraction without Multipole Expansion. | Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee, Charlie Chung-Ping Chen |
| 2001 | A Single-Multiplier Quadratic Interpolator for LNS Arithmetic. | Mark G. Arnold, Mark D. Winkel |
| 2001 | Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow. | Juan L. Aragn, Jos Gonzlez, Jos M. Garca, Antonio Gonzlez |
| 2001 | Fixed-outline Floorplanning through Better Local Search. | Saurabh N. Adya, Igor L. Markov |
| 2000 | Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. | Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh |