| 2013 | Practical template-algebraic side channel attacks with extremely low data complexity. | Yossef Oren, Ofir Weisse, Avishai Wool |
| 2013 | ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates. | Prashant J. Nair, Dae-Hyun Kim, Moinuddin K. Qureshi |
| 2013 | DNA-based molecular architecture with spatially localized components. | Richard A. Muscat, Karin Strauss, Luis Ceze, Georg Seelig |
| 2013 | Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems. | Janani Mukundan, Hillery C. Hunter, Kyu-Hyoun Kim, Jeffrey Stuecheli, Jos F. Martnez |
| 2013 | Red team vs. blue team hardware trojan analysis: detection of a hardware trojan on an actual ASIC. | Michael Muehlberghuber, Frank K. Grkaynak, Thomas Korak, Philipp Dunst, Michael Hutter |
| 2013 | Innovative instructions and software model for isolated execution. | Frank McKeen, Ilya Alexandrovich, Alex Berenzon, Carlos V. Rozas, Hisham Shafi, Vedvyas Shanbhogue, Uday R. Savagaonkar |
| 2013 | Whare-map: heterogeneity in "homogeneous" warehouse-scale computers. | Jason Mars, Lingjia Tang |
| 2013 | Improving the programmability of STHORM-based heterogeneous systems with offload-enabled OpenMP. | Andrea Marongiu, Alessandro Capotondi, Giuseppe Tagliavini, Luca Benini |
| 2013 | CPU transparent protection of OS kernel and hypervisor integrity with programmable DRAM. | Ziyi Liu, Jong-Hyuk Lee, Junyuan Zeng, Yuanfeng Wen, Zhiqiang Lin, Weidong Shi |
| 2013 | Security testing of a secure cache design. | Fangfei Liu, Ruby B. Lee |
| 2013 | An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms. | Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, Onur Mutlu |
| 2013 | Thin servers with smart pipes: designing SoC accelerators for memcached. | Kevin T. Lim, David Meisner, Ali G. Saidi, Parthasarathy Ranganathan, Thomas F. Wenisch |
| 2013 | A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA. | Shuo Li, Jamshaid Sarwar Malik, Shaoteng Liu, Ahmed Hemani |
| 2013 | GPUWattch: enabling energy optimizations in GPGPUs. | Jingwen Leng, Tayler H. Hetherington, Ahmed ElTantawy, Syed Zohaib Gilani, Nam Sung Kim, Tor M. Aamodt, Vijay Janapa Reddi |
| 2013 | Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures. | Jyu-Yuan Lai, Ting-Shuo Hsu, Po-Yu Chen, Chih-Tsun Huang, Yu-Hsun Chen, Jing-Jia Liou |
| 2013 | The locality-aware adaptive cache coherence protocol. | George Kurian, Omer Khan, Srinivas Devadas |
| 2013 | Quantum rotations: a case study in static and dynamic machine-code generation for quantum computers. | Daniel Kudrow, Kenneth Bier, Zhaoxia Deng, Diana Franklin, Yu Tomita, Kenneth R. Brown, Frederic T. Chong |
| 2013 | Microarchitectural mechanisms to exploit value structure in SIMT architectures. | Ji Kim, Christopher Torng, Shreesha Srinath, Derek Lockhart, Christopher Batten |
| 2013 | AutoPilot: message passing parallel programming for a cache incoherent embedded manycore processor. | Ben Kelly, William B. Gardner, Shorin Kyo |
| 2013 | A new perspective for efficient virtual-cache coherence. | Stefanos Kaxiras, Alberto Ros |
| 2013 | Many-core acceleration for model predictive control systems. | Satoshi Kawakami, Akihito Iwanaga, Koji Inoue |
| 2013 | Orchestrated scheduling and prefetching for GPGPUs. | Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar R. Iyer, Chita R. Das |
| 2013 | Utility-based acceleration of multithreaded applications on asymmetric CMPs. | Jos A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt |
| 2013 | An energy-efficient and scalable eDRAM-based register file architecture for GPGPU. | Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang |
| 2013 | Die-stacked DRAM caches for servers: hit ratio, latency, or bandwidth? have it all with footprint cache. | Djordje Jevdjic, Stavros Volos, Babak Falsafi |