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IEEE International Symposium on Rapid System Prototyping (was IEEE Symposium on Rapid Prototyping)

RSP

C

CORE rank

CORE rank (raw)

C

Fields of research

Software Engineering

Papers indexed

870

1990–2025

Papers per year

199046 peak2025

RSP papers

870 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2006Service Based Component Design Approach for Flexible Hardware/Software Interface Modeling.Lobna Kriaa, Aimen Bouchhima, Wassim Youssef, Frdric Ptrot, Anne-Marie Fouillart, Ahmed Amine Jerraya
2006Development of an FPGA-based System for Real-Time Simulation of.Eftichios Koutroulis, Kostas Kalaitzakis, Vasileios Tzitzilonis
2006Parameter-Specific FPGA Implementation of Edit-Distance Calculation.Kenneth B. Kent, Ryan B. Proudfoot, Yong Zhao
2006Performance Evaluation of an Adaptive FPGA for Network Applications.Christoforos Kachris, Stamatis Vassiliadis
2006A Case Study of Design Space Exploration for Embedded Multimedia Applications on SoCs.Isabelle Hurbain, Corinne Ancourt, Franois Irigoin, Michel Barreteau, Nicolas Museux, Frederic Pasquier
2006Dynamic Mapping of Runtime Information Models for Debugging Embedded Software.Philipp Graf, Klaus D. Mller-Glaser
2006Application-Level Memory Optimization for MPSoC.Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Pierre G. Paulin, Bruno Lavigueur
2006Formal Definitions of Simulation Interfaces in a Continuous/Discrete Co-Simulation Tool.Luiza Gheorghe, Faouzi Bouchhima, Gabriela Nicolescu, Hanifa Boucheneb
2006Rapid Resource-Constrained Hardware Performance Estimation.Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar
2006Creation and Validation of Embedded Assertion Statecharts.Doron Drusinsky, Man-tak Shing, Kadir Alpaslan Demir
2006Wcomp: a Multi-Design Approach for Prototyping Applications using Heterogeneous Resources.Daniel Cheung-Foo-Wo, Jean-Yves Tigli, Stephane Lavirotte, Michel Riveill
2006Generative Business Process Prototyping Framework.Ang Chen, Didier Buchs
2006Integrated Verification Approach during ADL-Driven Processor Design.Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2006Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter.Ccile Braunstein, Emmanuelle Encrenaz
2006Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs.Carsten Bieser, Klaus D. Mller-Glaser
2005Conference Committees.
2005Message from the Program Chairs.
2005Message from the Organizing Chair.
2005Message from the General Chairs.
2005Custom Instruction Filter Cache Synthesis for Low-Power Embedded Systems.Kugan Vivekanandarajah, Thambipillai Srikanthan
2005Dynamic Reconfiguration of IP-Based Systems.Markus Visarius, Andr Meisel, Markus Scheithauer, Wolfram Hardt
2005Rapid Development Methodology for Customized Middleware.Thomas Vergnaud, Jrme Hugues, Laurent Pautet, Fabrice Kordon
2005Optimization of Memory Allocation for Real-Time Video Processing on FPGA.Benny Thrnberg, Leif Olsson, Mattias O'Nils
2005Prototyping a Residential Gateway Using Xilinx ISE.S. W. Song, J. D. Zheng, William B. Gardner
2005Optimization Techniques for ADL-Driven RTL Processor Synthesis.Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
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