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Manfred Glesner

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

140

Venues

26

Active years

1986–2013

Best venue rank

A*

Where they publish

Papers

140 indexed papers, newest first.

YearVenueTitleAuthors
2013FPLAn event-based middleware for the remote management of runtime hardware reconfiguration.Franois Philipp, Manfred Glesner
2012FPLImplementation and outcomes of FPGA-based system design in Mongolian education.D. Erdenechimeg, Ts. Sugir, Franois Philipp, Manfred Glesner
2012FPL(GECO)Franois Philipp, Manfred Glesner
2011ASPLOSReconfigurable interconnect infrastructure for multi-FPGA-based adaptive multiprocessing systems.Faizal Arya Samman, Franois Philipp, Manfred Glesner
2011FPLMechanisms and Architecture for the Dynamic Reconfiguration of an Advanced Wireless Sensor Node.Franois Philipp, Manfred Glesner
2011FPLPipelined Floating-Point Architecture for a Phase and Magnitude Detector Based on CORDIC.Surapong Pongyupinpanich, Manfred Glesner
2011ISCASRF energy harvester design with autonomously adaptive impedance matching network based on auxiliary charge-pump rectifier.Ping Zhao, Manfred Glesner
2011RSPDesign of an autonomous platform for distributed sensing-actuating systems.Franois Philipp, Faizal Arya Samman, Manfred Glesner
2011RSPOn-chip efficient Round-Robin scheduler for high-speed interconnection.Surapong Pongyupinpanich, Manfred Glesner
2010FPLImproving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers.Leandro Mller, Peter Fischer, Fernando Moraes, Leandro Soares Indrusiak, Manfred Glesner
2009DATEA flexible floating-point wavelet transform and wavelet packet processor.Andre Guntoro, Manfred Glesner
2009FPLDesign and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes.Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2009FPLAn integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs.Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2009FPLTowards a unique FPGA-based identification circuit using process variations.Haile Yu, Philip Heng Wai Leong, Heiko Hinkelmann, Leandro Mller, Manfred Glesner, Peter Zipf
2008DATEAn Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs.Petru Bogdan Bacinschi, Tudor Murgan, Klaus Koch, Manfred Glesner
2008DATEComparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation.Massoud Momeni, Petru Bogdan Bacinschi, Manfred Glesner
2008DATEMulticast Parallel Pipeline Router Architecture for Network-on-Chip.Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
2008FPLCoarse-grained reconfiguration.Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jrgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jrgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2008FPLA lifting-based DWT and IDWT processor with multi-context configuration and normalization factor.Andre Guntoro, Manfred Glesner
2008FPLHigh-performance fpga-based floating-point adder with three inputs.Andre Guntoro, Manfred Glesner
2008FPLApplication-specific reconfigurable processors.Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Gtz Kappen, Tobias G. Noll
2008ISCASProcess variations aware robust on-chip bus architecture synthesis for MPSoCs.Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner
2008RSPA Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging Support.Heiko Hinkelmann, Andreas Reinhardt, Manfred Glesner
2008RSPBandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II.Christopher Spies, Peter Zipf, Manfred Glesner, Harald Klingbeil
2007DATEInteractive presentation: Executable system-level specification models containing UML-based behavioral patterns.Leandro Soares Indrusiak, Andreas Thuy, Manfred Glesner
2007FPLA Power Estimation Model for an FPGA-based Softcore Processor.Peter Zipf, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume, Tobias G. Noll
2007GLOBECOMA Scalable Resampling Architecture.Mihail Petrov, Manfred Glesner
2007GLOBECOMAn Efficient Fractional-Rate Interpolation Architecture.Mihail Petrov, Manfred Glesner
2006DACStatistical on-chip communication bus synthesis and voltage scaling under timing yield constraint.Sujan Pandey, Manfred Glesner
2006DATEA signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits.Oliver Soffke, Peter Zipf, Tudor Murgan, Manfred Glesner
2006FDLApplying Communication Patterns to Actor-Oriented Models.Andreas Thuy, Leandro Soares Indrusiak, Manfred Glesner
2006FPLMultitasking Support for Dynamically Reconfig Urable Systems.Heiko Hinkelmann, Andreas Gunberg, Peter Zipf, Leandro Soares Indrusiak, Manfred Glesner
2006FPLEnergy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture.Sujan Pandey, Manfred Glesner
2006ICCADA high-level compact pattern-dependent delay model for high-speed point-to-point interconnects.Tudor Murgan, Massoud Momeni, Alberto Garca Ortiz, Manfred Glesner
2006ICCDReduction of Crosstalk Pessimism using Tendency Graph Approach.Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier
2006ISCASEnergy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique.Sujan Pandey, Manfred Glesner
2005FPLOn-Chip Communication Topology Synthesis for a Shared Memory Architecture.Sujan Pandey, Manfred Glesner, Max Mhlhuser
2005FPLProgrammable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata.Peter Zipf, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred Glesner
2005FPLA Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata.Peter Zipf, Oliver Soffke, Andre Schumacher, Clemens Schlachta, Radu Dogaru, Manfred Glesner
2005GIEine weiterentwickelte quasi-statische adiabatische Logikfamilie.Clemens Schlachta, Oliver Soffke, Peter Zipf, Manfred Glesner
2005GIAbstrakte Modellierung der Eigenschaften von nanoelektronischen CNT-Elementen in SystemC.Peter Zipf, Oliver Soffke, Michael Velten, Manfred Glesner
2005ICCADDeadlock-free routing and component placement for irregular mesh-based networks-on-chip.Martin K. F. Schafer, Thomas Hollstein, Heiko Zimmer, Manfred Glesner
2005ISCASA linear model for high-level delay estimation in VDSM on-chip interconnects.Alberto Garca Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner
2005ISCASHigh level hardware/software communication estimation in shared memory architecture.Sujan Pandey, Heiko Zimmer, Manfred Glesner, Max Mhlhuser
2005ISCASFunctional modeling techniques for a wireless LAN OFDM transceiver.A. Petrov, Tudor Murgan, Peter Zipf, Manfred Glesner
2005RSPModeling and Prototyping of Communication Systems Using Java: A Case Study.Leandro Soares Indrusiak, Romualdo Begale Prudencio, Manfred Glesner
2004FPGAOn the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs.Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner
2004FPLIP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter.Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong-Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong
2004FPLThe XPP Architecture and Its Co-simulation Within the Simulink Environment.Mihail Petrov, Tudor Murgan, Frank May, Martin Vorbach, Peter Zipf, Manfred Glesner
2004FPLA Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals.Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner
2004IJCNNCPCA: a multiplierless neural PCA.Radu Dogaru, Ioana Dogaru, Manfred Glesner
2004ISCASDynamic power optimization of the trace-back process for the Viterbi algorithm.Mihail Petrov, Tudor Murgan, Abdulfattah Mohammad Obeid, Cristian Chitu, Peter Zipf, Jrg Brakensiek, Manfred Glesner
2004ISCASDesign of a reconfigurable AES encryption/decryption engine for mobile terminals.Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner
2004RSPRapid Prototyping of an Integrated Testing and Debugging Unit.Ralf Ludewig, Thomas Hollstein, Falko Schtz, Manfred Glesner
2003DATEUbiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues.Leandro Soares Indrusiak, Florian Lubitz, Ricardo Augusto da Luz Reis, Manfred Glesner
2003FDLSupporting Consistency Control between Functional and Structural Views in Interface-based Design Models.Leandro Soares Indrusiak, Ricardo Reis, Manfred Glesner
2003FPGAA granularity-based classification model for systems-on-a-chip.Stephan Bingemer, Peter Zipf, Manfred Glesner
2003FPLEvaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures.Tudor Murgan, Mihail Petrov, Alberto Garca Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard lkrug, Jrg Brakensiek
2003ICCADMoment-Based Power Estimation in Very Deep Submicron Technologies.Alberto Garca Ortiz, Lukusa D. Kabulepa, Tudor Murgan, Manfred Glesner
2003ISCASCompact image compression using simplicial and ART neural systems with mixed signal implementations.Radu Dogaru, Ioana Dogaru, Manfred Glesner
2003VLSIDTransition Activity Estimation for General Correlated Data Distributions.Alberto Garca Ortiz, Tudor Murgan, Manfred Glesner
2003RSPEmulation of Analog Components for the Rapid Prototyping of Wireless Baseband Systems.Ralf Ludewig, Alberto Garca Ortiz, Tudor Murgan, Juan Jess Ocampo Hidalgo, Manfred Glesner
2003RSPThe requirement for flexibility in IP-based designs increasesHardware Evaluation of Low Power Communication Mechanisms for Transport-Triggered Architectures.Thilo Pionteck, A. Garcya, Lukusa D. Kabulepa, Manfred Glesner
2002DACRegularization of hierarchical VHDL-AMS models using bipartite graphs.Jochen Mades, Manfred Glesner
2002DATEComparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments.Leandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis
2002DATEEstimation of Power Consumption in Encoded Data Buses.Alberto Garca Ortiz, Lukusa D. Kabulepa, Manfred Glesner
2002FPLFly - A Modifiable Hardware Compiler.Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto Garca Ortiz, Manfred Glesner
2002FPLA Framework for Teaching (Re)Configurable Architectures in Student Projects.Thilo Pionteck, Peter Zipf, Lukusa D. Kabulepa, Manfred Glesner
2002FPLHandling FPGA Faults and Configuration Sequencing Using a Hardware Extension.Peter Zipf, Manfred Glesner, Christine Bauer, Hans Wojtkowiak
2002ISCASPower reduction techniques for an OFDM burst synchronization core.Lukusa D. Kabulepa, Alberto Garca Ortiz, Manfred Glesner
2002ISCASDesign of an efficient OFDM burst synchronization scheme.Lukusa D. Kabulepa, Alberto Garca Ortiz, Manfred Glesner
2002ISCASA discrete algorithm for the regularization of hierarchical VHDL-AMS models.Jochen Mades, Diana Estvez Schwarz, Manfred Glesner
2002ISLPEDEfficient estimation of signal transition activity in MAC architectures.Alberto Garca Ortiz, Lukusa D. Kabulepa, Manfred Glesner
2002RSPRapid Prototyping of FPGA Based Floating Point DSP Systems.Chun Hok Ho, Monk-Ping Leong, Philip Heng Wai Leong, Jrgen Becker, Manfred Glesner
2002RSPPower Estimation Based on Transition Activity Analysis with an Architecture Precise Rapid Prototyping System.Ralf Ludewig, Alberto Garca Ortiz, Tudor Murgan, Manfred Glesner
2002RSPPrototyping of a High Performance Generic Viterbi Decoder.Abdulfattah Mohammad Obeid, Alberto Garca Ortiz, Ralf Ludewig, Manfred Glesner
2002RSPOn the Rapid Prototyping of Equalizers for OFDM Systems.Thilo Pionteck, N. Toender, Lukusa D. Kabulepa, Manfred Glesner, Tideya Kella
2001FPLEfficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures.Jrgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred Glesner
2001GLOBECOMFinite-precision analysis of an OFDM burst synchronization scheme.Lukusa D. Kabulepa, Manfred Glesner, Tideya Kella
2001ISCASA low power sinusoidal clock.Burkart Voss, Manfred Glesner
2001VTCLower bound on the accuracy of the CORDIC-based frequency offset compensation in burst oriented OFDM systems.Lukusa D. Kabulepa, Tideya Kella, Manfred Glesner
2001RSPPrototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems.Amar Mukherjee, Nitin Motgi, Jrgen Becker, A. Friebe, C. Habermann, Manfred Glesner
2000FCCMArchitecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems.Ahmad Alsolaim, Janusz A. Starzyk, Jrgen Becker, Manfred Glesner
2000FPLDReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications.Jrgen Becker, Thilo Pionteck, Manfred Glesner
2000FPLField Programmable Communication Emulation and Optimization for Embedded System Design.Frank-Michael Renner, Jrgen Becker, Manfred Glesner
2000ICASSPComputing discrete time-frequency distributions using principal component filter bank.Thuyen Le, Manfred Glesner
2000ICMLDirect Bayes Point Machines.Matthias Rychetsky, John Shawe-Taylor, Manfred Glesner
2000ISCASAn efficient filter bank architecture for the cross-term reduced processing of discrete time-frequency distributions.Thuyen Le, Manfred Glesner
2000ISCASRotating stall analysis using signal-adapted filter bank and Cohen's time-frequency distributions.Thuyen Le, Manfred Glesner
2000ISCASConfigurable VLSI-architectures for both standard DCT and shape-adaptive DCT in future MPEG-4 circuit implementations.Thuyen Le, Manfred Glesner
2000ISCASStatistical modelling of the MPEG-4 FlexMux.Ulrich Mayer, Jrgen Deicke, Manfred Glesner
2000ISCCEstimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams Connected to (R)CBR Channels.Ulrich Mayer, Jrgen Deicke, Manfred Glesner
2000PDPTAIP-based Application Mapping Techniques for Dynamically Reconfigurable Hardware Architectures.Jrgen Becker, Manfred Glesner
2000PDPTAFast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures.Jrgen Becker, Manfred Glesner, Ahmad Alsolaim, Janusz A. Starzyk
2000RSPSimulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications.Jrgen Becker, Lukusa D. Kabulepa, Frank-Michael Renner, Manfred Glesner
2000RSPHardware Accelerated Estimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams.Ulrich Mayer, Manfred Glesner
2000RSPAutomated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded Systems.Frank-Michael Renner, Jrgen Becker, Manfred Glesner
1999FPLDynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching.Tri Caohuu, Thuy Trong Le, Manfred Glesner, Jrgen Becker
1999ICASSPA data-driven scheme for the approximated computing of alias-free generalized discrete time-frequency distributions.Thuyen Le, Manfred Glesner
1999ICASSPA new flexible architecture for variable length DCT targeting shape-adaptive transform.Thuyen Le, Manfred Glesner
1999IJCNNPerceptrons revisited: the addition of a non-monotone recursion greatly enhances their representation and classification properties.Radu Dogaru, Marinel Alangiu, Matthias Rychetsky, Manfred Glesner
1999IJCNNOn the variance reduction of neural networks-experimental results for an automotive application.Stefan Ortmann, Matthias Rychetsky, Manfred Glesner
1999IJCNNSupport vector approaches for engine knock detection.Matthias Rychetsky, Stefan Ortmann, Manfred Glesner
1999IJCNNAccelerated training of support vector machines.Matthias Rychetsky, Stefan Ortmann, Michael Ullmann, Manfred Glesner
1999VLSIDDesign and Test of MEMs.Bernard Courtois, Jean-Michel Karam, Salvador Mir, Marcelo Lubaszewski, Vladimr Szkely, Mrta Rencz, Klaus Hofmann, Manfred Glesner
1999RSPCommunication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems.Frank-Michael Renner, Jrgen Becker, Manfred Glesner
1998DATEGeneration of Interconnect Topologies for Communication Synthesis.Michael Gasteier, Manfred Glesner, Michael Mnch
1998FPLPerspectives of Reconfigurable Computing in Research, Industry and Education.Jrgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner
1998FPLAn FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications.Frank-Michael Renner, Jrgen Becker, Manfred Glesner
1998RSPRun-Time Monitoring of Communication Activities in a Rapid Prototyping Environment.Andreas Kirschbaum, Jrgen Becker, Manfred Glesner
1998RSPRapid Prototyping of a Co-Processor Based Engine Knock Detection System.Andreas Kirschbaum, Stefan Ortmann, Manfred Glesner
1997DACCAD and Foundries for Microsystems.Jean-Michel Karam, Bernard Courtois, Hicham Boutamine, Paul Drake, Andrs Poppe, Vladimr Szkely, Mrta Rencz, Klaus Hofmann, Manfred Glesner
1997DATEGeneration of the HDL-A-model of a micromembrane from its finite-element-description.Klaus Hofmann, Manfred Glesner, Nicu Sebe, Anca Manuela Manolescu, Santiago Marco, Josep Samitier, Jean-Michel Karam, Bernard Courtois
1997DATEAutomatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystems.M. Lang, D. David, Manfred Glesner
1997FPLA prototyping environment for fuzzy controllers.Thomas Hollstein, Andreas Kirschbaum, Manfred Glesner
1997RSPRapid prototyping of communication architectures.Andreas Kirschbaum, Manfred Glesner
1997RSPHardware in-the-loop simulation-a rapid prototyping approach for designing mechatronics systems.Thuyen Le, Frank-Michael Renner, Manfred Glesner
1996DATEApplied design and analysis of microsystems.Jean-Michel Karam, Bernard Courtois, Andrs Poppe, Klaus Hofmann, Mrta Rencz, Manfred Glesner, Vladimr Szkely
1996FPLCAPpartx: Computer Aided Prototyping Partitioning for Xilinx FPGAs, a Hierarchical Partitioning Tool for Rapid Prototyping.Ulrike Ober, Hans-Jrgen Herpel, Manfred Glesner
1996ICIPImage coding with fuzzy region-growing segmentation.Alexander Steudel, Manfred Glesner
1996RSPRapid-Prototyping of a CAN-Bus Controller: A Case Study.Andreas Kirschbaum, Frank-Michael Renner, Alexander Wilmes, Manfred Glesner
1995FPLPrototype Generation of Application-Specific Embedded Controllers for Microsystems.Hans-Jrgen Herpel, Ulrike Ober, Manfred Glesner
1995FPLAdvanced Method for Industry Related Education with an FPGA Design Self-Learning Kit.U. Zahm, Thomas Hollstein, Hans-Jrgen Herpel, Norbert Wehn, Manfred Glesner
1995SACComparison of a heuristic method with a genetic algorithm for generation of compact rule based classifiers.Saman K. Halgamuge, Alain Brichard, Manfred Glesner
1995SACA sub Bayesian nearest prototype neural network with fuzzy interpretability for diagnosis problems.Saman K. Halgamuge, Christoph Grimm, Manfred Glesner
1995SACMultidimensional defuzzification - fast algorithms for the determination of crisp characteristic subsets.Thomas A. Runkler, Manfred Glesner
1995RSPRapid prototyping in microsystems development.Hans-Jrgen Herpel, Manfred Glesner, Horst Eggert, Wolfgang S, Martina Gorges-Schleuter, Wilfried Jakob
1994BMVCSystematic Methods for Multivariate Data Visualization and Numerical Assessment of Class Separability and Overlap in Automated Visual Industrial Quality Control.Andreas Knig, Olaf Bulmahn, Manfred Glesner
1994MASCOTSMCEMS Toolbox - A Hardware-in-the-Loop Simulation Environment for Mechatronic Systems.Hans-Jrgen Herpel, Michael Held, Manfred Glesner
1994SACAutomatic generation of a fuzzy classification system using fuzzy clustering methods.Harald Genther, Manfred Glesner
1994SACFuzzy neural fusion techniques for industrial applications.Saman K. Halgamuge, Manfred Glesner
1994SACDECADE - fast centroid approximation defuzzification for real time fuzzy control applications.Thomas A. Runkler, Manfred Glesner
1993ECRTSReal-Time System Prototyping Based on a Heterogeneous Multi-Processor Environment.Hans-Jrgen Herpel, Michael Held, Manfred Glesner
1992FPGAHigh Level Synthesis in an FPL-Based Computer Aided Prototyping Environment.Peter Poechmueller, Hans-Jrgen Herpel, Manfred Glesner, Fang Longsen
1991RSPRAMSES-a rapid prototyping environment for embedded control applications.Hans-Jrgen Herpel, Norbert Wehn, Manfred Glesner
1990IJCNNHandwritten pattern recognition with a binary associative memory.Werner Pchmller, Manfred Glesner
1988DACA Defect-Tolerant and Fully Testable PLA.Norbert Wehn, Manfred Glesner, K. Caesar, P. Mann, A. Roth
1988GIEntwurf eines systolischen Arrays in Wafer Scale Technik fr die digitale Signalverarbeitung.Manfred Glesner, M. Huch, Peter A. Ivey, T. Midwinter, Gabriele Saucier, Jacques Trilhe
1987DACThe ALGIC Silicon Compiler System: Implementation, Design Experience and Results.Johannes Schuck, Norbert Wehn, Manfred Glesner, G. Kamp
1986DACSCAT - a new statistical timing verifier in a silicon compiler system.Manfred Glesner, Johannes Schuck, R. B. Steck