| 2023 | Polynomial Formal Verification exploiting Constant Cutwidth. | Mohamed A. Nadeem, Jan Kleinekathfer, Rolf Drechsler |
| 2023 | HDLGen-ChatGPT Case Study: RISC-V Processor VHDL and Verilog Model - Testbench and EDA Project Generation. | Fearghal Morgan, John Patrick Byrne, Abishek Bupathi, Roshan George, Muhammad Adnan Elahi, Frank Callaly, Sean Kelly, Declan O'Loughlin |
| 2023 | ReDaML: A Modeling Language for DO-178C High-Level Requirements in Airspace Systems. | Henrique Amaral Misson, Rim Zrelli, Maroua Ben Attia, Felipe Gohring de Magalhaes, Gabriela Nicolescu |
| 2023 | Secured-by-design systems-on-chip: a MBSE Approach. | Raphale Milan, Loc Lagadec, Thotime Bollengier, Lilian Bossuet, Ciprian Teodorov |
| 2023 | SerIOS: Enhancing Hardware Security in Integrated Optoelectronic Systems. | Felipe G. Magalhaes, Mahdi Nikdast, Gabriela Nicolescu |
| 2023 | The Impact of Heterogeneous Logic on Adders and Multipliers in VTR. | Navid Jafarof, Kenneth B. Kent |
| 2023 | Extending Memory Compatibility with Yosys Front-End in VTR Flow. | Alireza Azadi, Amir Arjomand, Kenneth B. Kent |
| 2022 | ANN-based Performance Estimation of Embedded Software for RISC-V Processors. | Weiyan Zhang, Mehran Goli, Alireza Mahzoon, Rolf Drechsler |
| 2022 | Automatically Restructuring HDL Modules for Improved Reusability in Rapid Synthesis. | Jakob Wenzel, Christian Hochberger |
| 2022 | A Case for Second-Level Software Cache Coherency on Many-Core Accelerators. | Arthur Vians, Frdric Ptrot, Frdric Rousseau |
| 2022 | Machine Learning-Based Hard/Soft Logic Trade-offs in VTR. | Ritwik Sinha, Seyed Alireza Damghani, Kenneth B. Kent |
| 2022 | A framework that enables systematic analysis of mixed-signal applications on FPGA. | Gabriel Rutsch, Maximilian Groebner, Anthony Sanders, Konrad Maier, Wolfgang Ecker |
| 2022 | Early prototyping and testing of CERN LHC CMS high-granularity calorimeter slow-control system. | Martim Rosado, Stavros Mallios, Pedro Toms, Nuno Roma, Andr David |
| 2022 | Enhancing embedded AI-based object detection using multi-view approach. | Zijie Ning, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet |
| 2022 | TernaryNeRF: Quantizing Voxel Grid-based NeRF Models. | Seungyeop Kang, Sungjoo Yoo |
| 2022 | Marine Objects Detection Using Deep Learning on Embedded Edge Devices. | Dominique Heller, Mostafa Rizk, R. Douguet, Amer Baghdadi, Jean-Philippe Diguet |
| 2021 | An FPGA-based Emulation Platform for Edge Computing Node Design Exploration. | Theo Soriano, David Novo, Pascal Benoit |
| 2021 | Template-Driven and Hardware-Centric Cross-Domain E/E Architecture Simulation. | Kevin Neubauer, Leonard Masing, Michael Mahl, Jrgen Becker, Max E. Kramer, Clemens Reichmann |
| 2021 | Instruction Set Design Methodology for In-Memory Computing through QEMU-based System Emulator. | Kevin Mambu, Henri-Pierre Charles, Julie Dumas, Maha Kooli |
| 2021 | HyCo: A Low-Latency Hybrid Control Plane for Optical Interconnection Networks. | Felipe Ghring de Magalhes, Mahdi Nikdast, Fabiano Hessel, Odile Liboiron-Ladouceur, Gabriela Nicolescu |
| 2021 | FPGA Prototyping of Systolic Array-based Accelerator for Low-Precision Inference of Deep Neural Networks. | Soobeom Kim, Seunghwan Cho, Eunhyeok Park, Sungjoo Yoo |
| 2021 | Heterogeneous Logic Implementation for Adders in VTR. | Harpreet Kaur, Georgiy Krylov, Seyed Alireza Damghani, Kenneth B. Kent |
| 2021 | Implementing Rowhammer Memory Corruption in the gem5 Simulator. | Loc France, Florent Bruguier, Maria Mushtaq, David Novo, Pascal Benoit |
| 2021 | Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration. | Bruno Ferres, Olivier Muller, Frdric Rousseau |
| 2021 | Data Augmentation Framework for Smart Sensor System Development Using the Sensor-in-the-Loop Prototyping Platform. | Nils Bscher, Daniel Gis, Johann-Peter Wolff, Christian Haubelt |