| 2002 | Mathematical Methods in VLSI (Tutorial Abstract). | M. V. Atre, P. S. Subramanian, H. Narayanan |
| 2002 | A Framework for Design Space Exploration of Parameterized VLSI Systems. | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi |
| 2002 | Net Clustering Based Macrocell Placement. | Stelian Alupoaei, Srinivas Katkoori |
| 2002 | Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. | Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky |
| 2002 | Electronic Testing for SOC Designers (Tutorial Abstract). | Vishwani D. Agrawal, Michael L. Bushnell |
| 2002 | Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. | Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu |
| 2001 | A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification. | Jian-Kun Zhao, Jeffrey A. Newquist, Janak H. Patel |
| 2001 | A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits. | Sujit T. Zachariah, Sreejit Chakravarty |
| 2001 | Logic Synthesis for CPLDs and FPGAs with PLA-Style Logic Blocks. | Kenneth Yan |
| 2001 | On Fault-Simulation Through Embedded Memories On Large Industrial Designs. | Sitaram Yadavalli, Sandip Kundu |
| 2001 | Transmission Line Modeling by Modified Method of Characteristics. | Qinwei Xu, Pinaki Mazumder, Zheng-Fan Li |
| 2001 | Modeling of Nonuniform Interconnects by Using Differential Quadrature Method. | Qinwei Xu, Pinaki Mazumder, Mayukh Bhattacharya |
| 2001 | Vlsi Architectures For High-Speed Map Decoders. | Alexander Worm, Holger Lamm, Norbert Wehn |
| 2001 | Design Verification and Functional Testing of FiniteState Machines. | Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr |
| 2001 | Multilevel Logic Minimization Using Functional Don't Cares. | Lingli Wang, A. E. A. Almaini |
| 2001 | Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits. | Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal |
| 2001 | ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications. | G. Surendra, S. K. Nandy, Paul Sathya |
| 2001 | Application Specific Macro Based Synthesis. | Sujatha Sundararaman, Sriram Govindarajan, Ranga Vemuri |
| 2001 | Estimating Crosstalk From Vlsi Layouts. | V. Sankara Subramanian, C. P. Ravikumar |
| 2001 | Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. | Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul |
| 2001 | Partitioning Routing Area into Zones with Distinct Pins. | Koushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhattacharya, P. S. Dasgupta |
| 2001 | Dynamic Voltage Scheduling Using Adaptive Filtering of Workload Traces. | Amit Sinha, Anantha P. Chandrakasan |
| 2001 | Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. | Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly |
| 2001 | Design Of Multiple Attractor Gf (2p) Cellular AutomataFor Diagnosis Of Vlsi Circuits. | Biplab K. Sikdar, Purnabha Majumder, Parimal Pal Chaudhuri, Niloy Ganguly |
| 2001 | erformance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering. | G. Shrivastav, S. Mahapatra, V. Ramgopal Rao, J. Vasi, K. G. Anil, C. Fink, Walter Hansch, I. Eisele |