| 2001 | Efficient Synthesis of Array Intensive Computations onto FPGA Based Accelerators. | U. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary, Mahmut T. Kandemir |
| 2001 | Combination of Structural and State Analysis for Partial Scan. | Sameer Sharma, Michael S. Hsiao |
| 2001 | Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies. | Sabyasachi Sengupta, Somavalli Ramanathan, Biswadeep Chatterjee, Dibyendu Goswami |
| 2001 | The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes. | Vineet Sahula, C. P. Ravikumar |
| 2001 | Synthesis of System-on-a-chip for Testability. | Srivaths Ravi, Niraj K. Jha |
| 2001 | Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study. | Anupam Rastogi, M. Balakrishnan, Anshul Kumar |
| 2001 | System Level Testability Issues of Core Based System-on-a-Chip. | V. Ranganatha, R. Sunda |
| 2001 | Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies. | Anand Raghunathan, Sujit Dey |
| 2001 | High Frequency Behaviour Of Electron Transport In Silicon And Its Implication For Drain Conductance Of Mos Transistors. | B. Prasad, P. J. George, Chandra Shekhar |
| 2001 | Accurate Power Macro-modeling Techniques for Complex RTL Circuits. | Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar |
| 2001 | Application of Esterel for Modelling and Verification of Cachet Protocol on CRF Memory Model. | Siddharth R. Phanse, R. K. Shyamasundar |
| 2001 | Battery Life Estimation of Mobile Embedded Systems. | Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla Fabiana Chiasserini, Anand Raghunathan |
| 2001 | Repeater Insertion To Minimise Delay In Coupled Interconnects. | Dinesh Pamunuwa, Hannu Tenhunen |
| 2001 | Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations. | Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell |
| 2001 | Invited Paper: Extending Resolution Limits of IC Fabrication Technology: Demonstration by Device Fabrication and Circuit Performance. | Omkaram Nalamasu, Pat G. Watson, Raymond A. Cirelli, Jeff Bude, Isik C. Kizilyalli, Ross A. Kohler |
| 2001 | An On-Chip Coupling Capacitance Measurement Technique. | Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai |
| 2001 | Average Power in Digital CMOS Circuits using Least Square Estimation. | Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali |
| 2001 | Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics. | Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai, V. Ramgopal Rao |
| 2001 | A Code Transition Delay Model for ADC Test. | Sanjay Mohan, Michael L. Bushnell |
| 2001 | Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. | Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexandru Nicolau |
| 2001 | Low-Power Wireless Sensor Networks. | Rex Min, Manish Bhardwaj, Seong-Hwan Cho, Eugene Shih, Amit Sinha, Alice Wang, Anantha P. Chandrakasan |
| 2001 | Optimization and Analysis Techniques for the Deep Submicron Regime. | Noel Menezes, Sachin S. Sapatnekar |
| 2001 | Functional Verification of Programmable DSP Cores. | Mahesh Mehendale, Santhosh Kumar Amanna |
| 2001 | Architecture of Reconfigurable a Low Power Gigabit AT Switch. | Abhijit M. Lele, S. K. Nandy |
| 2001 | Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. | Marcello Lajolo, Matteo Sonza Reorda, Massimo Violante |