| 2000 | A Transistor Level Placement Tool for Custom Cell Generation. | Ranjit K. Dash, T. Pramod, Vinita Vasudevan, M. Ramakrishna |
| 2000 | Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits. | Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta |
| 2000 | An ASIC for Cellular Automata Based Message Authentication. | Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta |
| 2000 | Trends in Communication Technology and its Impact on Semiconductor. | Santanu Das |
| 2000 | On the Transistor Sizing Problem. | Abhijit Das |
| 2000 | Manufacturing and Test Considerations in System-On-Chip Designs. | Manuel A. d'Abreu |
| 2000 | A Methodology for the Placement and Optimization of Decoupling Capacitors for Gigahertz Systems. | Jinseong Choi, Sungjun Chun, Nanju Na, Madhavan Swaminathan, Larry D. Smith |
| 2000 | An Efficient Hierarchical Fault Isolation Technique for Mixed-Signal Boards. | Sasikumar Cherubal, Abhijit Chatterjee |
| 2000 | Specification and Design of a Quasi-Delay-Insensitive Java Card. | Fu-Chiung Cheng, Chuin-Ren Wang |
| 2000 | Theory and Applications of Cellular Automata for VLSI Design and Testing. | Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar |
| 2000 | Design and Analysis of Power Distribution Networks with Accurate RLC Models. | Rajat Chaudhry, Rajendran Panda, Tim Edwards, David T. Blaauw |
| 2000 | Retargetable Functional Simulator Using High Level Processor Models. | Subhash Chandra, Rajat Moona |
| 2000 | IP Reuse in System on a Chip Design. | Raul Camposano, Warren Savage, John Chilton |
| 2000 | New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. | Melvin A. Breuer, Sandeep K. Gupta |
| 2000 | Performance and Functional Verification of Microprocessors. | Pradip Bose, Jacob A. Abraham |
| 2000 | EDA-The Next Generation. | Ajoy K. Bose |
| 2000 | Hierarchical Error Diagnosis Targeting RTL Circuits. | Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita |
| 2000 | Resource-Constrained Compaction of Sequential Circuit Test Sets. | Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy |
| 2000 | Topological Routing Amidst Polygonal Obstacles. | Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
| 2000 | Convergence Issues in Resonant Tunneling Diode Circuit Simulation. | Mayukh Bhattacharya, Pinaki Mazumder |
| 2000 | Zero-Aliasing Space Compression using a Single Periodic Output and its Application to Testing of Embedded Cores. | Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gssel |
| 2000 | Choice of Tests for Logic Verification and Equivalence Checking. | Vishwani D. Agrawal |
| 1999 | POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing. | Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik |
| 1999 | A Comparative Study of Pseudo Stuck-At and Leakage Fault Model. | Sujit T. Zachariah, Sreejit Chakravarty |
| 1999 | A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults. | Jue Wu, Elizabeth M. Rudnick |