| 1999 | Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic Circuits. | Shugang Wei, Kensuke Shimizu |
| 1999 | Modeling Crosstalk in Resistive VLSI Interconnections. | Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang |
| 1999 | Test Generation for Analog Circuits Using Partial Numerical Simulation. | Pramodchandran N. Variyam, Junwei Hou, Abhijit Chatterjee |
| 1999 | Diagnostic Test Pattern Generation for Analog Circuits Using Hierarchical Models. | Sudip Chakrabarti, Abhijit Chatterjee |
| 1999 | Superscalar Processor Validation at the Microarchitecture Level. | Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen |
| 1999 | Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations. | Pradip A. Thaker, Mona E. Zaghloul, Minesh B. Amin |
| 1999 | Timed Circuit Synthesis Using Implicit Methods. | Robert A. Thacker, Wendy Belluomini, Chris J. Myers |
| 1999 | A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. | Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury |
| 1999 | Optimal Voltages and Sizing for Low Power. | Mircea R. Stan |
| 1999 | Formal Verification of a Snoop-Based Cache Coherence Protocol Using Symbolic Model Checking. | Srivatsan Srinivasan, Parminder Singh Chhabra, Praveen Kumar Jaini, Adnan Aziz, Lizy Kurian John |
| 1999 | A Low-Complexity, Reduced-Power Viterbi Algorithm. | P. K. Singh, Sriram Jayasimha |
| 1999 | Simulation and Modeling of a Multicast ATM Switch. | Ajoy C. Siddabathuni, M. Balakrishnan |
| 1999 | Design for Manufacturing in the Semiconductor Industry: The Litho/Design Workshops. | Franklin M. Schellenberg |
| 1999 | The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. | Prashant Saxena, Peichen Pan, C. L. Liu |
| 1999 | Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons. | Ingo Sander, Axel Jantsch |
| 1999 | Low Power Design Methodologies for Systems-on-Chips. | Kaushik Roy, Anand Raghunathan, Sujit Dey |
| 1999 | Verification of Systems-on-Chip Designs. | Rahul Razdan, Apurva Kalia, Manu Lauria |
| 1999 | Improving the Diagnosability of Digital Circuits. | C. P. Ravikumar, Manish Sharma, R. K. Patney |
| 1999 | Hierarchical Delay Fault Simulation. | C. P. Ravikumar, Ajay Mittal |
| 1999 | Efficient Translation of Statecharts to Hardware Circuits. | S. Ramesh |
| 1999 | Synthesis of Configurable Architectures for DSP Algorithms. | S. Ramanathan, V. Visvanathan, S. K. Nandy |
| 1999 | Built-In Self-Test for Systems on Silicon. | Janusz Rajski, Jerzy Tyszer, Sanjay Patel |
| 1999 | Processor Modeling for Hardware Software Codesign. | V. Rajesh, Rajat Moona |
| 1999 | COST Circuit Optimization SysTem in ASIC Library Development Environment. | C. S. Raghu, Suravi Bhowmik, Poorvaja Ramani, S. Sundaram |
| 1999 | Automatic Insertion of Gated Clocks at Register Transfer Level. | Nithya Raghavan, Venkatesh Akella, Smita Bakshi |