| 1999 | Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization. | Pradeep Prabhakaran, Prithviraj Banerjee, Jim E. Crenshaw, Majid Sarrafzadeh |
| 1999 | VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | Invited Talk: The Information Appliance and Its Interface to the Analog World: Easy - Or Not So Easy. | Robert A. Pease |
| 1999 | A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata. | Kolin Paul, P. Dutta, Dipanwita Roy Chowdhury, Prasanta Kumar Nandi, Parimal Pal Chaudhuri |
| 1999 | Formal Verification of an ARM Processor. | Vishnu A. Patankar, Alok Jain, Randal E. Bryant |
| 1999 | A Semi-Digital Delay Locked Loop for Clock Skew Minimization. | Joonbae Park, Yido Koo, Wonchan Kim |
| 1999 | Design and Implementation of Viterbi Decoder Using FPGAs. | Bupesh Pandita, Subir K. Roy |
| 1999 | Optimal Retiming for Initial State Computation. | Peichen Pan, Guohua Chen |
| 1999 | A Low-Power Digital Camera-on-a-Chip Implemented in CMOS Active Pixel Approach. | Bedabrata Pain, Guang Yang, Brita Olson, Timothy Shaw, Monico Ortiz, Julie Heynssens, Chris Wrigley, Charlie Ho |
| 1999 | Synthesis of DMA Controllers from Architecture Independent Descriptions of HW/SW Communication Protocols. | Mattias O'Nils, Axel Jantsch |
| 1999 | Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis. | Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell |
| 1999 | Recent Advances in BDD Based Representations for Boolean Functions: A Survey. | Amit Narayon |
| 1999 | Analyzing Forced Oscillators with Multiple Time Scales. | Onuttom Narayan, Jaijeet S. Roychowdhury |
| 1999 | Characterizing Individual Gate Power Sensitivity in Low Power Design. | Unni Narayanan, Georgios I. Stamoulis, Rabindra K. Roy |
| 1999 | Satisfiability-Based Detailed FPGA Routing. | Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar |
| 1999 | Compact, Ultra Low Power, Programmable Continuous-Time Filter Banks for Feedback Cancellation in Hearing Aid. | Kavita Nair, Ramesh Harjani |
| 1999 | VLSI Signal Processing in FPGAs. | Sudip Nag, H. K. Verma, Kaushik Roy |
| 1999 | Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs. | D. V. R. Murthy, Seetharaman Ramachandran, S. Srinivasan |
| 1999 | Efficient Scheduling Techniques for ROBDD Construction. | Rajeev Murgai, Jawahar Jain, Masahiro Fujita |
| 1999 | Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. | Noel Menezes, Chung-Ping Chen |
| 1999 | Empirical Computation of Reject Ratio in VLSI Testing. | Shashank K. Mehta, Sharad C. Seth |
| 1999 | Low Power Code Generation of Multiplication-free Linear Transforms. | Mahesh Mehendale, Sunil D. Sherlekar |
| 1999 | Efficient Simulation for Hierarchical and Partitioned Circuits. | Peter M. Maurer |
| 1999 | A New Approach for CMOS Op-Amp Synthesis. | Pradip Mandal, V. Visvanathan |
| 1999 | A Complete Characterization of Path Delay Faults through Stuck-at Faults. | Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell |