| 1999 | Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms. | M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale |
| 1999 | Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued Cases. | Luca Macchiarulo, Pierluigi Civera |
| 1999 | Performance Driven Synthesis for Pass-Transistor Logic. | Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns |
| 1999 | Invited Talk: Practical Use of Formal Verification - Where are we? Where do we go? | Ramayya Kumar |
| 1999 | Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. | Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan |
| 1999 | Hierarchical Conditional Dependency Graphs for Mutual Exclusiveness Identification. | Apostolos A. Kountouris, Christophe Wolinski |
| 1999 | Sequential Multi-Valued Network Simplification using Redundancy Removal. | Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1999 | nvited Talk: Micro-2010: Lead Microprocessor for 2010 - Myth or Reality? | Manpreet S. Khaira |
| 1999 | TECHMIG: A Layout Tool for Technology Migration. | Pradip K. Kar, Subir K. Roy |
| 1999 | An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits. | Zbigniew Kalbarczyk, Janak H. Patel, Myeong S. Lee, Ravishankar K. Iyer |
| 1999 | New and Exact Filling Algorithms for Layout Density Control. | Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky |
| 1999 | Interconnect Optimization Strategies for High-Performance VLSI Designs. | Andrew B. Kahng, Sudhakar Muddu, Egino Sarto |
| 1999 | Improved Effective Capacitance Computations for Use in Logic and Layout Optimization. | Andrew B. Kahng, Sudhakar Muddu |
| 1999 | Mini-Tutorial: IC Layout and Manufacturability: Critical Links and Design Flow Implications. | Andrew B. Kahng |
| 1999 | Design Considerations and Implementation of a High Performance Dynamic Register File. | Rajiv V. Joshi, Wei Hwang |
| 1999 | Sequential Chaotic Annealing and its Application to Multilayer Channel Routing. | Jayadeva |
| 1999 | FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model. | Rathish Jayabharathi, Manuel A. d'Abreu, Jacob A. Abraham |
| 1999 | Test-Vector Prediction of M-Testable Iterative Arrays. | M. Jamoussi |
| 1999 | Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis. | Ludovic Jacomme, Frdric Ptrot, Rajesh K. Bawa |
| 1999 | Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. | Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita |
| 1999 | A Test Generator for Segment Delay Faults. | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
| 1999 | Exact Output Response Computation of RC Interconnects under Polynomial Input Waveforms. | Satrajit Gupta, Lalit M. Patnaik |
| 1999 | A State Assignment Scheme Targeting Performance and Area. | B. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai |
| 1999 | Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells. | Avaneendra Gupta, John P. Hayes |
| 1999 | Invited Talk: Quantum Computation. | Lov K. Grover |