| 2000 | A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores. | Karthikeyan Madathil, Jagdish C. Rao, Subash Chandar G., Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar |
| 2000 | Performance Analysis of Systems with Multi-Channel Communication Architectures. | Kanishka Lahiri, Sujit Dey, Anand Raghunathan |
| 2000 | Clock Selection for Performance Optimization of Control-Flow Intensive Behaviors. | Kamal S. Khouri, Niraj K. Jha |
| 2000 | Cost Trade-Offs in System On Chip Designs. | Jitendra Khare, Hans T. Heineken, Manuel d'Abreu |
| 2000 | Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. | Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake |
| 2000 | A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25m SOI Technology. | Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang |
| 2000 | Evaluation of Various Routing Architectures for Multi-FPGA Boards. | Sushil Chandra Jain, Shashi Kumar, Anshul Kumar |
| 2000 | Test Transformation to Improve Compaction by Statistical Encoding. | Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | Built-In Self-Test in Mixed-Signal ICs: A DTMF Macrocell. | Gloria Huertas, Diego Vzquez, Adoracin Rueda, Jos L. Huertas |
| 2000 | Core Based ASIC Design. | Frank P. Higgins, Sudipta Bhawmik |
| 2000 | Relating Data Characteristics to Transition Activity in High-Level Static CMOS Design. | Russell E. Henning, Chaitali Chakrabarti |
| 2000 | Analog Circuits for Wireless Communications. | Ramesh Harjani |
| 2000 | Processor Evaluation in an Embedded Systems Design Environment. | T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik |
| 2000 | Fast Error Diagnosis for Combinational Verification. | Aarti Gupta, Pranav Ashar |
| 2000 | A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures. | Sriram Govindarajan, Vinoo Srinivasan, Preetham Lakshmikanthan, Ranga Vemuri |
| 2000 | Timing Analysis with Implicitly Specified False Paths. | Eugene Goldberg, Alexander Saldanha |
| 2000 | Formal Verification of Synthesized Mixed Signal Designs Using *BMDs. | Abhijit Ghosh, Ranga Vemuri |
| 2000 | A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity. | Hideo Fujiwara |
| 2000 | Spectral Theory of Disjunctive Decomposition for Balanced Boolean Functions. | Bogdan J. Falkowski, Sudha Kannurao |
| 2000 | Routing on Switch Matrix Multi-FPGA Systems. | Abdel Ejnioui, N. Ranganathan |
| 2000 | Design Partitioning on Single-Chip Emulation Systems. | Abdel Ejnioui, N. Ranganathan |
| 2000 | Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television Applications. | Santanu Dutta, Deepak Singh, Essam Abu-Ghoush, Vijay Mehra |
| 2000 | Interconnect Statistical Modeling: Structures and Measurement Methodologies. | Akis Doganis |
| 2000 | COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server Systems. | Robert P. Dick, Niraj K. Jha |
| 2000 | A Fast Algorithm for Computing the Euler Number of an Image and its VLSI Implementation. | Sabyasachi Dey, Bhargab B. Bhattacharya, Malay Kumar Kundu, Tinku Acharya |