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International Conference on VLSI Design

VLSID

National

CORE rank

CORE rank (raw)

National: India

Fields of research

Distributed Computing and Systems Software

Papers indexed

3,530

1992–2026

Papers per year

1992175 peak2026

VLSID papers

3,530 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
1998Incremental Autojogging using Range Spaces.Cyrus Bamji, Ravi Varadarajan
1998An Improved Cost Heuristic for Transistor Sizing.Cyrus Bamji, Manjit Borah
1998Arbitrary Precision Arithmetic - SIMD Style.Srinivasan Balakrishnan, Soumitra Kumar Nandy
1998Peripheral Partitioning and Tree Decomposition for Partial Scan.Arun Balakrishnan, Srimat T. Chakradhar
1998Automated AC (Timing) Characterization for Digital Circuit Testing.S. Balajee, Ananta K. Majhi
1998A Framework for a Parallel Architecture Dedicated to Soft Computing.Giuseppe Ascia, Vincenzo Catania
1998Top-Down Approach to Technology Migration for Full-Custom Mask Layouts.Zinaida V. Apanovich, Alexander G. Marchuk
1998On-Chip Signature Checking for Embedded Memories.Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1998Hybrid Testing Schemes Based on Mutual and Signature Testing.Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1998An Embedded Processor for Integrated Navigation Receiver.Anteneh Alemu Abbo
1997Optimal Design of Checksum-Based Checkers for Fault Detection in Linear Analog Circuits.Heebyung Yoon, Abhijit Chatterjee, Joseph L. A. Hughes
1997Shake And Bake: A Method of Mapping Code to Irregular DSPs.Thomas Charles Wilson, Gary William Grewal
1997Design For Testability: Today And In The Future.Tomas W. Williams
1997Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs.Madhavi Vootukuru, Ranga Vemuri, Nand Kumar
1997Pseudoduplication - An ACOB Technique for Single-Ended Circuits.Bapiraju Vinnakota, Ramesh Harjani, Wooyoung Choi
1997Distributed Diagnostic Simulation of Stuck-At Faults in Sequential Circuits.Srikanth Venkataraman, W. Kent Fuchs
1997FLYER: Fast Fault Simulation of Linear Analog Circuits Using Polynomial Waveform and Perturbed State Representation.Pramodchandran N. Variyam, Abhijit Chatterjee
1997A Novel Hierarchical Test Generation Method for Processors.Raghuram S. Tupuri, Jacob A. Abraham
1997Dynamic Power Management for Microprocessors: A Case Study.Vivek Tiwari, Ryan Donnelly, Sharad Malik, Ricardo Gonzalez
1997Formal Verification of Digital Systems.Gitanjali Swamy
1997T2: HW-SW Codesign.P. A. Subrahmanyam, R. Gupta, B. S. Rao
1997Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation.Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal
1997Primitive Path Delay Fault Identification.Mukund Sivaraman, Andrzej J. Strojwas
1997Synthesis for Logical Initializability of Synchronous Finite State Machines.Montek Singh, Steven M. Nowick
1997Macro Block Based FPGA Floorplanning.Jianzhong Shi, Akash Randhar, Dinesh Bhatia
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