| 1997 | Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial. | Abhijit Chatterjee, Naveena Nagi |
| 1997 | Deriving Signal Constraints to Accelerate Sequential Test Generation. | Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler |
| 1997 | Inductive Verification of Sequential Circuits with a Datapath. | I. Chakrabarti, Dipankar Sarkar, Arun K. Majumdar |
| 1997 | SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits. | Premal Buch, Ernest S. Kuh |
| 1997 | Characterization and Implicit Identification of Sequential Indistinguishability. | Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs |
| 1997 | A Design Technique of TSC Checker for Borden's Code. | Gosta Pada Biswas, Indranil Sengupta |
| 1997 | Design of t-UED/AUED Codes from Berger's AUED Code. | Gosta Pada Biswas, Idranil Sen Gupta |
| 1997 | A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits. | Sudipta Bhawmik, Indradeep Ghosh |
| 1997 | Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit. | Debashis Bhattacharya, Smith Freeman, Bill Lin |
| 1997 | A Parallel Architecture for Video Compression. | Partha Sarathi Bhattacharjee, Sajal K. Das, Debashis Saha, D. Roychowdhury, Parimal Pal Chaudhuri |
| 1997 | Reconfigurable Computing. | Dinesh Bhatia |
| 1997 | A General Reconfiguration Technique for Fault Tolerant Processor Architectures. | Eshwar Belani, Ravi Mittal |
| 1997 | (Quasi-) Linear Path Delay Fault Tests for Adders. | Bernd Becker, Rolf Drechsler, Sudhakar M. Reddy |
| 1997 | Decision Diagrams in Synthesis - Algorithms, Applications and Extensions. | Bernd Becker, Rolf Drechsler |
| 1997 | Architectures for Arithmetic over GF(2 | Rana Barua, Samik Sengupta |
| 1997 | A Method for Synthesizing Area Efficient Multilevel PTL Circuits. | Subir Bandyopadhyay, Arunita Jaekel, Graham A. Jullien |
| 1997 | An Expert System Approach to Analog Circuit Synthesis. | V. Ravindra Babu, Baquer Mazhari, M. M. Hasan |
| 1997 | Design of a VLSI Hardware PET Decoder. | Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili |
| 1997 | Low-Power Design by Hazard Filtering. | Vishwani D. Agrawal |
| 1997 | A Novel Reconfigurable Co-Processor Architecture. | Gaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar |
| 1997 | Efficient Implementation of Multiple On-Chip Signature Checking. | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
| 1996 | Routing using implicit connection graphs [VLSI design. | Si-Qing Zheng, Joon Shik Lim, S. Sitharama Iyengar |
| 1996 | A simple yet effective genetic approach for the orientation assignment on cell-based layout. | Jin-Tai Yan |
| 1996 | A Very High Gain Bandwidth Product Fully Differential Amplifier. | J. Weiss, B. Majoux, Grard Bouvier |
| 1996 | Maximum power estimation for CMOS circuits using deterministic and statistic approaches. | Chuan-Yu Wang, Kaushik Roy |