| 1996 | Mixed-Signal Design for Test. | Bapiraju Vinnakota, Ramesh Harjani |
| 1996 | SUBGEN: a genetic approach for subcircuit extraction. | Narayanan Vijaykrishnan, N. Ranganathan |
| 1996 | Clock-Skew Constrained Cell Placement. | Natesan Venkateswaran, Dinesh Bhatia |
| 1996 | Instruction Level Power Analysis and Optimization of Software. | Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee |
| 1996 | Fast Algorithms for Computer IDDQ Tests for Combination Circuits. | Paul J. Thadikaran, Sreejit Chakravarty |
| 1996 | Identifying Redundant Path Delay Faults in Sequential Circuits. | Ramesh C. Tekumalla, Premachandran R. Menon |
| 1996 | A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts. | Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny berg, Axel Jantsch, Hannu Tenhunen |
| 1996 | LUT-based FPGA Technology Mapping using Permissible Functions. | Takayuki Suyama, Hiroshi Sawada, Akira Nagoya |
| 1996 | Combined Effect of Grain Boundary Depletion and PolySi/Oxide Interface Depletion on Drain Characteristics of a p-MOSFET. | R. P. Suresh, P. Venugopal, S. Tamizh Selvam, S. Potla |
| 1996 | Distributed logic simulation: time-first evaluation vs. event driven algorithms. | S. Sundaram, Lalit M. Patnaik |
| 1996 | Medium access control and air-interface subsystem for an indoor wireless ATM network. | Mani B. Srivastava |
| 1996 | Behavioral Modeling of an ATM Switch using SpecCharts. | A Sriram, Fadi J. Kurdahi |
| 1996 | A 20MHz CMOS Variable Gain Amplifier. | C. Srinivasan, K. Radhakrishna Rao |
| 1996 | Diagnosis of parametric path delay faults. | Mukund Sivaraman, Andrzej J. Strojwas |
| 1996 | Bipartitioning for Hybrid FPGA-Software Simulatio. | Ashutosh Singla, Thomas M. Conte |
| 1996 | A multiplier generator for Xilinx FPGAs. | Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar |
| 1996 | Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation. | J. Shu, Thomas Charles Wilson, Dilip K. Banerji |
| 1996 | Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs. | Jatan C. Shah, Sachin S. Sapatnekar |
| 1996 | VLSI/WSI Designs for Folded Cube-Connected Cycles Architectures. | M. P. Sebastian, P. S. Nagendra Rao, Lawrence Jenkins |
| 1996 | Hierarchical Probablistic Diagnosis of MCMs on Large-Area Substrates. | Koppolu Sasidhar, Abhijit Chatterjee |
| 1996 | Representation and Synthesis of Interface of a Circuit for its Reuse. | Santonu Sarkar, Anupam Basu, Arun K. Majumdar |
| 1996 | Designing Systems On Silicon: A Digital Spread Spectrum Pager. | S. Samel, Bert Gyselinckx, Ivo Bolsens, Hugo De Man |
| 1996 | Low Power Design. | Kaushik Roy, R. K. Roy |
| 1996 | Synthesis of Testable Pipelined Datapaths Using Genetic Search. | C. P. Ravikumar, Vikram Saxena |
| 1996 | Genetic Algorithms for Scan Path Design. | C. P. Ravikumar, Rajamani Rajarajan |