| 1996 | Estimation of Power from Module-level Netlists. | C. P. Ravikumar, Mukul R. Prasad, Lavmeet S. Hora |
| 1996 | VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder. | Ranjeet Ranade, Sanjay Bhandari, A. N. Chandorkar |
| 1996 | A systolic architecture for LMS adaptive filtering with minimal adaptation delay. | S. Ramanathan, V. Visvanathan |
| 1996 | Test generation for mixed-signal devices using signal flow graphs. | Rajesh Ramadoss, Michael L. Bushnell |
| 1996 | Challenges in Low Power Microprocessor Design. | Suresh Rajgopal |
| 1996 | Dynamic test Sequence compaction for Sequential Circuits. | Anand Raghunathan, Srimat T. Chakradhar |
| 1996 | A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. | D. V. Poornaiah, P. V. Ananda Mohan |
| 1996 | On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1996 | Automatic Synthesis of Speed-Independent Circuits from Signal Transition Graph Specifications. | Sung-Bum Park, Takashi Nanya |
| 1996 | Statistical path delay fault coverage estimation for synchronous sequential circuits. | Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas |
| 1996 | A Rule-Based Approach for Improving Allocation of Filter Structures in HLS. | Johnny berg, Jouni Isoaho, Peeter Ellervee, Axel Jantsch, Ahmed Hemani |
| 1996 | A study of composition schemes for mixed apply/compose based construction of ROBDDs. | Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Synchronous Controller Models for Synthesis from Communicating VHDL Processes. | Naren Narasimhan, Ranga Vemuri, Jay Roy |
| 1996 | Programmable cellular automata based testbed for fault diagnosis in VLSI circuits. | Sukumar Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri |
| 1996 | Design tradeoffs in high speed multipliers and FIR filters. | Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin |
| 1996 | Elimination of Dynamic Hazards from Signal Transition Graphs. | Radhakrishna Nagalla, Graham R. Hellestrand |
| 1996 | On More Efficient Combinational ATPG Using Functional Learning. | Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell |
| 1996 | Architecture of a VLSI Chip for Modeling Amino Acid Sequence in Proteins. | S. Mitra, S. Das, Parimal Pal Chaudhuri, Sukumar Nandi |
| 1996 | An Analytical Delay Model Based on Boolean Process. | Yinghua Min, Zhuxing Zhao, Zhongcheng Li |
| 1996 | Low power realization of FIR filters using multirate architectures. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1996 | Is Compiled Simulation Really Faster than Interpreted Simulation? | Peter M. Maurer |
| 1996 | Design of high performance two stage CMOS cascode op-amps with stable biasing. | Pradip Mandal, V. Visvanathan |
| 1996 | Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach. | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose |
| 1996 | On test coverage of path delay faults. | Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal |
| 1996 | Instruction-Set Modeling for ASIP Code Generation. | Rainer Leupers, Peter Marwedel |