| 1996 | Methods for Dynamic Test Vector compaction in Sequential Test Generation. | Timothy John Lambert, Kewal K. Saluja |
| 1996 | A high-speed 32-bit parallel correlator for spread spectrum communication. | Shriram Kulkarni, Pinaki Mazumder, George I. Haddad |
| 1996 | A tree matching chip. | Vamsi Krishna, Abdel Ejnioui, N. Ranganathan |
| 1996 | Register Transfer Level Synthesis: From Theory to Practice. | Kurt Keutzer, Sharad Malik |
| 1996 | A Hierarchical Register Optimization Algorithm for Behavioral Synthesis. | Srinivas Katkoori, Ranga Vemuri, Jay Roy |
| 1996 | VaWiRAM: a variable width random access memory module. | Lizy Kurian John |
| 1996 | Multilevel Factorization Technique for Pass Transistor Logic. | Arunita Jaekel, Graham A. Jullien, Subir Bandyopadhyay |
| 1996 | Improving accuracy in path delay fault coverage estimation. | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
| 1996 | CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. | Reiner W. Hartenstein, Jrgen Becker, Rainer Kress, Helmut Reinig |
| 1996 | Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs. | Fran Hanchek, Shantanu Dutt |
| 1996 | Self timed division and square-root extraction. | Alain Guyot, Marc Renaudin, Bachar El-Hassan, Volker Levering |
| 1996 | VLSI Implementation of DSP Architectures. | A. Ratan Gupta, V. Visvanathan |
| 1996 | On Moment-Based Metric for Optimal Termination of Transmission Line Interconnects. | Rohini Gupta, Byron Krauter, Lawrence T. Pileggi |
| 1996 | KANSYS: a CAD tool for analog circuit synthesis. | S. K. Gupta, M. M. Hasan |
| 1996 | Hardware Software Co-Design of Embedded Systems. | Rajesh Gupta |
| 1996 | Parallel concurrent path-delay fault simulation using single-input change patterns. | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
| 1996 | Dual rail static CMOS architecture for wave pipelining. | G. Enrique Fernandez, R. Sridhar |
| 1996 | The New Electronics Industry. | Thomas J. Engibou |
| 1996 | Geometric bipartitioning problem and its applications to VLSI. | Parthasarathi Dasgupta, Anup K. Sen, Subhas C. Nandy, Bhargab B. Bhattacharya |
| 1996 | Syndrome signature in output compaction for VLSI BIST. | Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak |
| 1996 | Does retiming affect redundancy in sequential circuits? | Debesh Kumar Das, Bhargab B. Bhattacharya |
| 1996 | Channel routing in Manhattan-diagonal model. | Sandip Das, Bhargab B. Bhattacharya |
| 1996 | A Graph-Based Approach to the Synthesis of Multi-Chip Module Architectures. | Raghava V. Cherabuddi, Jijun Chen, Magdy A. Bayoumi |
| 1996 | Cellular automata based architecture of a database query processor. | Santanu Chattopadhyay, S. Mitra, Parimal Pal Chaudhuri |
| 1996 | Low-cost DC built-in self-test of linear analog circuits using checksums. | Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi |