| 1996 | Parallel simulated annealing strategies for VLSI cell placement. | John A. Chandy, Prithviraj Banerjee |
| 1996 | Mobile Communications: Demands on VLSI Technology, Design and CAD. | Anantha P. Chandrakasan, Kurt Keutzer, A. Khandekar, S. L. Maskara, B. D. Pradhan, Mani B. Srivastava |
| 1996 | Ultra low power digital signal processing. | Anantha P. Chandrakasan |
| 1996 | Design for high-speed testability of stuck-at faults. | Tapan J. Chakraborty, Vishwani D. Agrawal |
| 1996 | An Efficient Test Generation Technique for Sequential Circuits with Repetitive Sub-Circuits. | Dhruva R. Chakrabarti, Ajai Jain |
| 1996 | A low power video encoder with power, memory and bandwidth scalability. | Navin Chaddha, Mohan Vishwanath |
| 1996 | VLSI in Mobile Communication. | Robert W. Brodersen, Rajeev Jain |
| 1996 | Low-Power, Low-Voltage BiCMOS Comparators for Approximately 200MHz, 8bit Operation. | Andrea Boni, Carlo Morandi |
| 1996 | Cubical CAMP for minimization of Boolean functions. | Nripendra N. Biswas, C. Srikanth, James Jacob |
| 1996 | Behavioral Synthesis of Complex Parallel Controllers. | Krzysztof Bilinski, Erik L. Dagless, Jonathan M. Saul |
| 1996 | A micropower analog hearing aid on low voltage CMOS digital process. | A. B. Bhattacharyya, Ram Singh Rana, S. K. Guha, Rajendar Bahl, Sneh Anand, M. J. Zarabi, P. A. Govindacharyulu, Vivek Gupta, Vivek Mohan, Jatin Roy, Amul Atri |
| 1996 | A VLSI architecture for cellular automata based parallel data compression. | Subarna Bhattacharjee, J. Bhattacharya, U. Raghavendra, Debashis Saha, Parimal Pal Chaudhuri |
| 1996 | Synchronous Test Generation Model for Asynchronous Circuits. | Savita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy |
| 1996 | Retiming with logic duplication transformation: theory and an application to partial scan. | Arun Balakrishnan, Srimat T. Chakradhar |
| 1996 | Sequential Circuits with combinational Test Generation Complexity. | Arun Balakrishnan, Srimat T. Chakradhar |
| 1996 | Multi-way partitioning of VLSI circuits. | Prathima Agrawal, Balakrishnan Narendran, Narayanan Shivakumar |
| 1996 | Characteristic polynomial method for verification and test of combinational circuits. | Vishwani D. Agrawal, David Lee |
| 1996 | Science, Technology, and the Indian Society. | Vishwani D. Agrawal |
| 1996 | An Enhanced Macromodel for a CMOS Operational Amplifier for HDL Implementation. | Sudhir Aggarwal |
| 1996 | Practical Test and DFT for Next Generation VLSI. | Jacob A. Abraham, Gopi Ganapathy |
| 1996 | A Novel BIST Architecture With Built-in Self Check. | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
| 1996 | Testing Analogue Circuits by A C Power Supply Voltage. | Abu Khari bin A'Ain, A. H. Bratt, A. P. Dorey |
| 1995 | A new fuzzy-clustering-based approach for two-way circuit partitioning. | Jin-Tai Yan, Pei-Yung Hsiao |
| 1995 | MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. | Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy |
| 1995 | A modular systolic architecture for delayed least mean squares adaptive filtering. | V. Visvanathan, S. Ramanathan |