| 1995 | Parallel test generation with low communication overhead. | Sivaramakrishnan Venkatraman, Sharad C. Seth, Prathima Agrawal |
| 1995 | An HOL based framework for design of correct high level synthesizers. | B. M. Subraya, Anshul Kumar, Shashi Kumar |
| 1995 | CODAC-a characterization system for digital and analog circuits. | Nagaraj Subramanyam, K. G. Praveen, Ramesh Ramani, D. Suryanarayana |
| 1995 | Functional test generation for non-scan sequential circuits. | Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal |
| 1995 | SAGA: the first general-purpose on-line arithmetic co-processor. | Ali Skaf, Alain Guyot |
| 1995 | Object oriented data modeling for VLSI/CAD. | Anoop Singhal, Chi-Yuan Lo |
| 1995 | Retiming of synchronous circuits with variable topology. | Sven Simon, Ralf Bucher, Josef A. Nossek |
| 1995 | An asynchronous algorithm for sequential circuit test generation on a network of workstations. | James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal |
| 1995 | A graph approach to DFT hardware placement for robust delay fault BIST. | Imtiaz P. Shaik, Michael L. Bushnell |
| 1995 | Genetic multiway partitioning. | Khushro Shahookar, Pinaki Mazumder |
| 1995 | Static RAM generators with automated characterization techniques for a 0.5 micron triple-metal embedded array. | Puneet Sawhney, Haroon Rasheed |
| 1995 | Synchronization of communicating modules and processes in high level synthesis. | Santonu Sarkar, Anupam Basu, Arun K. Majumdar |
| 1995 | Functional clock schedule optimization. | Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1995 | VLSI implementation of variable resolution image compression. | Hossein Sahabi, Anup Basu, Mark Fiala |
| 1995 | A genetic approach to test application time reduction for full scan and partial scan circuits. | Elizabeth M. Rudnick, Janak H. Patel |
| 1995 | HISCOAP: a hierarchical testability analysis tool. | C. P. Ravikumar, Hemant Joshi |
| 1995 | Test generation for cyclic combinational circuits. | Anand Raghunathan, Pranav Ashar, Sharad Malik |
| 1995 | A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology. | Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh |
| 1995 | Circuit optimization for minimisation of power consumption under delay constraint. | S. C. Prasad, Kaushik Roy |
| 1995 | Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. | D. V. Poornaiah, P. V. Ananda Mohan |
| 1995 | VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes. | Luca Penzo, Donatella Sciuto, Cristina Silvano |
| 1995 | Fully asynchronous, robust, high-throughput arithmetic structures. | Priyadarsan Patra, Donald S. Fussell |
| 1995 | Computing area and wire length efficient routes for channels. | Rajat Kumar Pal, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal |
| 1995 | Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs. | A. Pal, R. K. Gorai, V. V. S. S. Raju |
| 1995 | A general graph theoretic framework for multi-layer channel routing. | Rajat Kumar Pal, A. K. Datta, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal |