| 1995 | Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. | Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng |
| 1995 | CVD-diamond substrates for multi-chip modules (MCMs). | Hameed A. Naseem, Ajay P. Malshe, Rajan A. Beera, M. Shahid Haque, William D. Brown, Len W. Schaper |
| 1995 | Efficient multisine testing of analog circuits. | Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham |
| 1995 | Svoboda-Tung division with no compensation. | Luis A. Montalvo, Alain Guyot |
| 1995 | Combined optimization of area and testability during state assignment of PLA-based FSM's. | Chunduri Rama Mohan, Partha Pratim Chakrabarti |
| 1995 | Implementation of design functions by available devices: a new algorithm. | Raj S. Mitra, Partha S. Roop, Anupam Basu |
| 1995 | A consistent labeling approach to hardware software partitioning. | Raj S. Mitra, Mahmood G. Qadir, Anupam Basu |
| 1995 | AATMA: an algorithm for technology mapping for antifuse-based FPGAs. | Mahesh Mehendale, M. K. Ram Prasad |
| 1995 | An efficient automatic test generation system for path delay faults in combinational circuits. | Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal |
| 1995 | A fast algorithm to test planar topological routability. | Andrew Lim, Sartaj K. Sahni, Venkat Thanvantri |
| 1995 | Formal synthesis of circuits with a simple handshake protocol. | Ramayya Kumar, Thomas Kropf, Klaus Schneider |
| 1995 | Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis. | Alok Kumar, Anshul Kumar, M. Balakrishnan |
| 1995 | A fast-multiplier generator for FPGAs. | Suthikshn Kumar, Kevin E. Forward, Marimuthu Palaniswami |
| 1995 | Transmission line model parameters for very high speed VLSI interconnects in MCMs using FEM with special elements. | S. Y. Kulkarni, K. D. Patil, K. V. V. Murthy |
| 1995 | A single chip, pipelined, cascadable, multichannel, signal processor. | S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta |
| 1995 | Analysis of temperature dependence of Si-Ge HBT. | G. Hari Rama Krishna, Amit K. Aditya, Nirmal B. Chakrabarti, Swapna Banerjee |
| 1995 | JAGUAR: a high speed VLSI chip for JPEG image compression standard. | Mario Kovac, N. Ranganathan |
| 1995 | A new methodology for the design of low-cost fail safe circuits and networks. | B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh |
| 1995 | Testability-oriented channel routing. | Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar |
| 1995 | Design of a highly reconfigurable interconnect for array processors. | Lizyamma Kurian, Daniel Brewer, Eugene John |
| 1995 | A highly testable ASIC for telephone signaling. | P. Jayalakshmi, S. Vidya, S. Krishnakumar, K. Ravisankar, P. Kumar |
| 1995 | Efficient variable ordering and partial representation algorithm. | Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross |
| 1995 | A differential built-in current sensor design for high speed IDDQ testing. | Jason P. Hurst, Adit D. Singh |
| 1995 | Statistical methods for delay fault coverage analysis. | Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell |
| 1995 | A novel CMOS monolithic analog multiplier with wide input dynamic range. | George A. Hadgis, P. R. Mukund |