| 2025 | Advancing Rehabilitation Through Low Weight Hand Assistive System: Design and Impact Analysis. | Kushagra Singh, Kafil Abbas Momin, Anshul V. Patil, Madhav Rao |
| 2025 | Advancing Neural Network Performance with Probabilistic Computing for ReLU Function. | Amit Singh, Amit Kumar Jangid, B. Srinivasu |
| 2025 | Physical Insights into the Leakage Mechanisms Governing the Scaling Trends in 4H-SiC Based Junctionless FETs. | Jaspreet Singh, Aakash Kumar Jain, Mamidala Jagadesh Kumar |
| 2025 | HapticGuide: Interactive Wearable Braille Guide for Enhancing Visual Education. | Divyansh Singhal, Yash Gupta, Daksh Sharma, Chinmay Sultania, Madhav Rao |
| 2025 | Optimal Respiratory Rate Estimation with mmWave Sensing Using PYNQ System-on-Chip Platform. | Mohammed Musayyeb Sherwani, Mohammad Abdul Azeem, Mohammed Usman, Siddique Ahmad, Mujeev Khan, R. Shamim, Mohd Wajid |
| 2025 | Tunnel Magnetoresistance in Strained L10-FeAu Perpendicular Magnetic Tunnel Junction. | Rouf Rahman Sheikh, Ram Krishna Ghosh |
| 2025 | NSGA-RM: NSGA-II Evolved Performance Optimized Non-Homogeneous Recursive Polynomial Multiplier Architectures. | Daksh Sharma, D. R. Vasanthi, Sanampudi Gopala Krishna Reddy, Madhav Rao |
| 2025 | RISC-V Based Secure Processor Architecture for Return Address Protection. | Lalit Sharma, Neeraj Goel |
| 2025 | OwlsEye: Real-Time Low-Light Video Instance Segmentation on Edge and Exploration of Fixed-Posit Quantization. | Gaurav Shah, Abhinav Goud, Zaqi Momin, Joycee Mekie |
| 2025 | MAGIC-Based High-Speed Adders for in-Memory Computing Using Memristors. | Shri Janani Senthil, B. Srinivasu |
| 2025 | An SRAM-Based Multi-Operand Architecture Implementing Multi-Bit Boolean Functions Using in-Memory Periphery Computing. | Dhayan Dhananjaya Senanayake, Priyanshu Tyagi, Sparsh Mittal, Rekha Singhal |
| 2025 | DuRTL - Information Flow Analysis Tool for Register Transfer Level Hardware Designs. | Lutz Schammer, Gianluca Martino, Grschwin Fey |
| 2025 | TRANSPOSE: Circuit Transformations for Power Side-Channel Security at Register Transfer Level. | Nilotpola Sarma, Anuj Singh Thakur, Chandan Karfa |
| 2025 | Precision Clock Generation with Reference Clock Loss Tolerant Dynamic Tuning to Enable Crystal Less SSD. | Pikul Sarkar, Nitin Gupta, Pallat Aravind, Bhavin Odedara, Dror Shahar |
| 2025 | Interconnect Optimization for Timing and Power [IOTAP]. | Sourav Saha, Sagar Rana, Keshav Patil, Nagamaheswar Harivelam Srinivas Gari |
| 2025 | Physical Synthesis Optimization Prediction Using Machine Learning. | Sourav Saha, Anmol Khatri, Lalit Arora, Raj Yadav, Rakshit Bazaz |
| 2025 | Constructing Rectilinear Steiner Minimum Tree with Conditional Generative Adversarial Network. | Kritanta Saha, Pritha Banerjee, Susmita Sur-Kolay |
| 2025 | Boosting System-on-Chip Performance Through AI-Assisted Optimization Using Compositional Neural Networks. | Priyatam Roy, Surinder Sood |
| 2025 | BMC Engine Sequencing with Graph Neural Network Embeddings of Hardware Circuits. | Soumik Guha Roy, Adriz Chanda, Prateek Ganguli, Sumana Ghosh, Ansuman Banerjee, Raj Kumar Gajavelly, Sudhakar Surendran |
| 2025 | Atrial Flutter Detection System by AdEx Encoded Lead-II ECG. | Sushmi R, Priya K, Binsu J. Kailath |
| 2025 | 8GHz Multi-Phase Ring VCO Design with Wide Tuning Range for SerDes Applications in 6nm FinFET Process. | Ravuru Vasudeva Reddy, Siva Kumar Rapina, Siddhartha Hazra, K. Sarangam |
| 2025 | Enhancing Reliability and Energy Efficiency in Network-on-Chip Architectures through Hybrid Sorting Algorithm-Based Core Mapping. | B. Naresh Kumar Reddy, Srinivasulu Jogi, Yellapragada Charan Krishna |
| 2025 | Layer-Specific Hardware Pooling Designs for CNN Accelerators. | Vinay Rayapati, Mahati Basavaraju, Madhav Rao |
| 2025 | Hardware Implementation of Blind Decoding of Downlink Control Information for 5G. | Y. Anu rajarajeswari, Nitin Chandrachoodan, Anji Babu Vadapalli, J. Klutto Milleth |
| 2025 | FPUGen: A FrameWork to Generate Custom Floating Point FMA Accelerators on FPGAs. | Himanshu Rai, Aishwarya Sridhar, Wolfgang Ecker, Nanditha Rao |