| 2026 | A Fast-Transient, Low Quiescent Controller on a 16nm Integrated Voltage Regulator. | Anup J. Deka, Biswarup Rana, Shivansh Pandey, Shobhit Tyagi |
| 2026 | A 3nm Silicon Proven Mechanism to Eliminate Ground Bounce Impact for High-Precision Analog HVM Trim in Digital Processors. | Anup J. Deka, Balabrahmachari Matcha, Sanjay Singh, Subbu Manam |
| 2026 | Machine Learning Power Side-Channel Attack on SNOW-V. | Deepak, Rahul Balout, Anupam Golder, Suparna Kundu, Angshuman Karmakar, Debayan Das |
| 2026 | MIRAGE: Micro-Ring-Assisted General Engine with Phase-Error Compensation for Scalable Full-Range Matrix-Vector Multiplication. | Priyabrata Dash, Dharanidhar Dang |
| 2026 | Universal Formal Verification Approach for Modular Reduction Circuits. | Jiteshri Dasari, Maciej J. Ciesielski |
| 2026 | ASIC Design for a Hybrid Approximate Floating-Point Adder with Enhanced Carry Prediction Logic. | Sridhar C, Aniruddha Kanhe |
| 2026 | Bipolar Silicon Synapse for Bidirectional Spiking Neural Networks. | Tamal Chowdhury, Pradip Mandal |
| 2026 | Low-Power Tunable Band-Pass Filter Using Unipolar Oxide TFT Technology for Wearable Applications. | Vaishali Choudhary, Suyash Shrivastava, Pydi Ganga Bahubalindruni |
| 2026 | XR-NPE: High-Throughput Mixed-Precision SIMD Neural Processing Engine for Extended Reality Perception Workloads. | Tejas Chaudhari, Akarsh J, Tanushree Dewangan, Mukul Lokhande, Santosh Kumar Vishvakarma |
| 2026 | An Energy Efficient Pulse Accumulator Circuit (PAC) Based Multi-Bit Time Domain Compute in-Memory Architecture. | Subhradip Chakraborty, Dinesh Kushwaha |
| 2026 | AAMLA: An Autonomous Agentic Framework for Memory-Aware LLM-Aided Hardware Generation. | Rajat Bhattacharjya, Juhee Sung, Hangyeol Jung, Hyunwoo Oh, Arnab Sarkar, Mohsen Imani, Nikil D. Dutt |
| 2026 | FPGA Optimized Pipelined Modulo Computation Architecture Leveraging Primitive Instantiation and Placement Constraints for Efficient Logic Packing. | Suprabhat Bhattacharjee, Ayan Palchaudhuri |
| 2026 | Attack on a PUF-Based Secure Binary Neural Network. | Bijeet Basak, Nupur Patil, Kurian Polachan, Srinivas Vivek |
| 2026 | Balanced Cascade: Free-Flowing Microfluidic Lab-On-Chip for Generating Serial Dilutions. | Tapalina Banerjee, Sudip Poddar, Bhargab B. Bhattacharya |
| 2026 | Accelerated IDP and EnMod-DP Hybrid Models for Robust Evacuation Navigation in Cyber-Physical Human Environments: *Benchmarking Serial vs. Parallel Architectures on Heterogeneous Grids. | G. Balaji, Sadanand Venkataraman, Mahendravarman M, Santhi Natarajan, G. Ravi Prakash Iyer |
| 2026 | Scaling Limits and Reliability Challenges of Nanoscale GaN HEMTs: A Path Toward Advanced Node Benchmarking for DC and RF Applications. | Shivansh Awasthi, Vikas Kumar, Ankur Gupta |
| 2026 | A Fully Integrated High-PSRR LDO with Cascaded NMOS-PMOS Buffer Architecture in 180 nm CMOS. | Kaire Anupama, Patri Sreehari Rao |
| 2026 | PIDArc: Physics-Informed Deaggregated Architecture for Enhanced Aging-Aware Leakage Power Estimation for FinFET Logic Cells. | Mohammad Rehan Akhtar, Zia Abbas |
| 2025 | Multi-Object Detection Through Meta-Training in Resource-Constrained UAV-Based Surveillance Applications. | Abhishek Yadav, Vyom Kumar Gupta, Kethireddy Harshith Reddy, Masahiro Fujita, Binod Kumar |
| 2025 | CMOSP18 FD-SOI Technology Based MCU Achieving High Performance of 1.2GHz Using High Speed, Optimized Leakage & High Density Tightly Coupled Memory (TCM). | Praveen Verma, Anuj Dhillon, Ashfaque Ahmed, Yagnesh Vaderiya, Chandan Singh, Veenita Kumari, Harshit Sharma |
| 2025 | TOGGLE6.0: A 4.8Gbps Next Generation Area and Power Efficient Transceiver for Flash Memory Interface. | Hari Vijay Venkatanarayanan, Rustum Prasad Sahu, Maheswara Alamuru, Ergam Reddy Battini, Syed Mohammed Haroon, Saurav Suman, Deepika Mallela, Sanjeeb Kumar Ghosh, Billy Koo |
| 2025 | PAF-Enc: Position Affine Encoding to Reduce Bit-Flips in Non-Volatile Main Memories. | Swati Upadhyay, Hemangee K. Kapoor |
| 2025 | Optimization of Sub-Threshold Standard Cells for Energy Efficient Designs. | Vardhan Suroshi, Karthik B. K, Vikram Kannur, Vinay Reddy, Madhura Purnaprajna |
| 2025 | Startup Circuit for Relaxation Oscillators with Low Functional Current and Minimal Area. | Anubhav Srivastava, Sadique Mohammad Iqbal, Divya Tripathi, Saurabh Goyal |
| 2025 | Design of Manchester Carry Chain Hybrid Adder for MASH 1-1-1 Delta Sigma Modulator for Fractional-N Frequency Synthesizers. | Abhinav S, Busam Karthikeya, Ishan Acharyya, Anushka Tripathi, Abhishek Srivastava |