| 2007 | A Power and Area Efficient Maximum Likelihood Detector Implementation for High Throughput MIMO Systems. | Jong Hun Han, Ahmet T. Erdogan, Tughrul Arslan |
| 2007 | Temperature-limited microprocessors: Measurements and design implications. | Hendrik F. Hamann, Alan J. Weger, James A. Lacey, Zhigang Hu, Pradip Bose, Erwin B. Cohen, Jamil A. Wakil |
| 2007 | Tutorial T7B: RF Analysis and Simulation with Focus on RF SiP Methodology. | Sanjay Gupta, Taranjit Kukal, Alok Tripathi, Raja Mitra, Ashish Patni, Siddarth Shetty |
| 2007 | STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
| 2007 | A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes. | Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary |
| 2007 | Convergence of Nanoelectronics and Living Cells: A New Frontier for Diagnostics and Therapy? | Roberto Guerrieri |
| 2007 | Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation. | Ratnakar Goyal, Sachin Shrivastava, Harindranath Parameswaran, Parveen Khurana |
| 2007 | Power Reduction in VLIW Processor with Compiler Driven Bypass Network. | Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda |
| 2007 | Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes. | Matteo Giaconia, Marco Macchetti, Francesco Regazzoni, Kai Schramm |
| 2007 | Synthesizing "Verification Aware" Models: Why and How? | Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayashi |
| 2007 | Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions. | Zhaohui Fu, Sharad Malik |
| 2007 | Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture. | Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov |
| 2007 | Reusing Learned Information in SAT-based ATPG. | Grschwin Fey, Tim Warode, Rolf Drechsler |
| 2007 | Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. | Nikil D. Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha |
| 2007 | Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes. | Ashish Dobhal, Vishal Khandelwal, Ankur Srivastava |
| 2007 | Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence. | Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava |
| 2007 | Embedded Support Vector Machine : Architectural Enhancements and Evaluation. | Soumyajit Dey, Monu Kedia, Niket Agarwal, Anupam Basu |
| 2007 | Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
| 2007 | Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST. | Suresh Kumar Devanathan, Michael L. Bushnell |
| 2007 | Calibration Based Methods for Substrate Modeling and Noise Analysis for Mixed-Signal SoCsc. | Sankar P. Debnath, Ganesh P. Kumar, Sukumar Jairam |
| 2007 | Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections. | Masoud Daneshtalab, A. Pedram, Mohammad Hossein Neishaburi, Mohammad Riazati, Ali Afzali-Kusha, Siamak Mohammadi |
| 2007 | Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques. | Claas Cornelius, Frank Grassert, Siegmar Koppe, Dirk Timmermann |
| 2007 | Tutorial IND2B: Structured Embedded Configuration and Test. | C. J. Clark |
| 2007 | Online Dynamic Voltage Scaling using Task Graph Mapping Analysis for Multiprocessors. | Pravanjan Choudhury, P. P. Chakrabarti, Rajeev Kumar |
| 2007 | An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function. | Qikai Chen, Arjun Guha, Kaushik Roy |