| 2005 | A New Asymmetric Skewed Buffer Design for Runtime Leakage Power Reduction. | Yu-Shiang Lin, Dennis Sylvester |
| 2005 | Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. | Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar |
| 2005 | Electromigration-Aware Physical Design of Integrated Circuits. | Jens Lienig, Gran Jerke |
| 2005 | Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores. | Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan |
| 2005 | A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems. | Haris Lekatsas, Jrg Henkel, Venkata Jakkula, Srimat T. Chakradhar |
| 2005 | Design of Multi-GHz Asynchronous Pipelined Circuits in MOS Current-Mode Logic. | Tin Wai Kwan, Maitham Shams |
| 2005 | Off-Line Testing of Asynchronous Circuits. | Deepali Koppad, Alexandre V. Bystrov, Alexandre Yakovlev |
| 2005 | A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC Systems. | Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan |
| 2005 | Active Noise Cancellation Using Aggressor-Aware Clamping Circuit for Robust On-Chip Communication. | Atul Katoch, Maurice Meijer, Sanjeev K. Jain |
| 2005 | A Novel Specification Based Test Pattern Generation Using Genetic Algorithm and Wavelets. | P. Kalpana, K. Gunavathi |
| 2005 | Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. | Rajiv V. Joshi, S. S. Kang, N. Zamdmar, Anda Mocuta, Ching-Te Chuang, J. A. Pascual-Gutirrez |
| 2005 | SoC Design Methodology: A Practical Approach. | Atul Jain, Anindya Saha, Jagdish Rao |
| 2005 | Integrated On-Chip Storage Evaluation in ASIP Synthesis. | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
| 2005 | A Nanosensor Array-Based VLSI Gas Discriminator. | Kevin M. Irick, Wei Xu, Narayanan Vijaykrishnan, Mary Jane Irwin |
| 2005 | Non-Manhattan Routing Using a Manhattan Router. | Edward Hursey, Nikhil Jayakumar, Sunil P. Khatri |
| 2005 | On-Line Synthesis for Partially Reconfigurable FPGAs. | Renqiu Huang, Ranga Vemuri |
| 2005 | A Reconfigurable Oscillator Topology for Dual-Band Operation. | Tien-Ling Hsieh, Ranjit Gharpurey |
| 2005 | Energy Efficient Hardware Synthesis of Polynomial Expressions. | Anup Hosangadi, Farzan Fallah, Ryan Kastner |
| 2005 | A Methodology and Tooling Enabling Application Specific Processor Design. | Andreas Hoffmann, Frank Fiedler, Achim Nohl, Surender Parupalli |
| 2005 | Automatic Device Layout Generation for Analog Layout Retargeting. | Roy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Chuanjin Richard Shi |
| 2005 | A 160MSPS 8-Bit Pipeline Based ADC. | Samiran Halder, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Swapna Banerjee |
| 2005 | A System-Level Alternate Test Approach for Specification Test of RF Transceivers in Loopback Mode. | Achintya Halder, Soumendu Bhattacharya, Ganesh Srinivasan, Abhijit Chatterjee |
| 2005 | A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm | Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey |
| 2005 | Floorplan-Based Crosstalk Estimation for Macrocell-Based Designs. | Suvodeep Gupta, Srinivas Katkoori, Hariharan Sankaran |
| 2005 | Lazy Constraints and SAT Heuristics for Proof-Based Abstraction. | Aarti Gupta, Malay K. Ganai, Pranav Ashar |