DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks.

Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen

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