Erik Jan Marinissen
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
98
Venues
8
Active years
1998–2025
Best venue rank
A*
Where they publish
Papers
98 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ETS | Extendable E | Po-Yao Chuang, Erik Jan Marinissen |
| 2025 | ETS | European Test Symposium Teams: an Anniversary Snapshot. | Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilrd Enyedi, Iulia Stefan, Ovidiu Stan, Cosmina Corches, Zebo Peng, Petru Eles, Rolf Drechsler, S. Eggersgl, Grschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Po-Yao Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, Stefano Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, Patrick Girard, Marcello Traiola, Arnaud Virazel, Fernando Fernandes dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letcia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, Fabian Luis Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, Anurup Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand |
| 2025 | ITC | Chiplets' Die-to-Die Interconnect Repair Language (IRL). | Po-Yao Chuang, Erik Jan Marinissen |
| 2025 | ITC | Chiplet Interconnect Test and Repair. | Po-Yao Chuang, Cheng-Wen Wu, Erik Jan Marinissen |
| 2024 | ETS | Silent Data Corruption: Test or Reliability Problem? | Erik Jan Marinissen, Harish Dattatraya Dixit, Ronald Shawn Blanton, Aaron Kuo, Wei Li, Subhasish Mitra, Chris Nigh, Ruben Purdy, Ben Kaczer, Dishant Sangani, Pieter Weckx, Philippe J. Roussel, Georges G. E. Gielen |
| 2024 | ETS | New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405. | Erik Jan Marinissen, Adrian Evans, Po-Yao Chuang, Martin Keim, Anshuman Chandra |
| 2024 | ETS | Test and Repair Improvements for UCIe. | Tsung-Hsuan Wang, Po-Yao Chuang, Francesco Lorenzelli, Erik Jan Marinissen |
| 2024 | ETS | Design-for-Test for Intermittent Faults in STT-MRAMs. | Sicong Yuan, Mohammad Amin Yaldagard, Hanzhi Xun, Moritz Fieback, Erik Jan Marinissen, Woojin Kim, Siddharth Rao, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui |
| 2024 | ITC | Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment? | Sicong Yuan, Hanzhi Xun, Woojin Kim, Siddharth Rao, Erik Jan Marinissen, Sebastien Couet, Moritz Fieback, Mottaqiallah Taouil, Said Hamdioui |
| 2024 | VTS | IEEE Std P3405: New Standard-under-Development for Chiplet Interconnect Test and Repair. | Erik Jan Marinissen, Vineet Pancholi, Po-Yao Chuang, Martin Keim |
| 2023 | DATE | Device-Aware Test for Back-Hopping Defects in STT-MRAMs. | Sicong Yuan, Mottaqiallah Taouil, Moritz Fieback, Hanzhi Xun, Erik Jan Marinissen, Gouri Sankar Kar, Sidharth Rao, Sebastien Couet, Said Hamdioui |
| 2023 | ETS | Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications. | Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen |
| 2023 | ITC | Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures. | Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen |
| 2023 | ITC | Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs. | Sicong Yuan, Ziwei Zhang, Moritz Fieback, Hanzhi Xun, Erik Jan Marinissen, Gouri Sankar Kar, Sidharth Rao, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui |
| 2023 | VTS | Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. | Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen |
| 2023 | VTS | IP Session on Chiplet: Design, Assembly, and Test. | Bapi Vinnakota, Jaber Derakhshandeh, Eric Beyne, Erik Jan Marinissen, Sreejit Chakravarty |
| 2021 | DATE | Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM. | Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui |
| 2021 | ETS | Speeding up Cell-Aware Library Characterization by Preceding Simulation with Structural Analysis. | Francesco Lorenzelli, Zhan Gao, Joe Swenton, Santosh Malagi, Erik Jan Marinissen |
| 2021 | ETS | Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring. | Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Alkis A. Hatzopoulos, Makoto Nagata, Erik Jan Marinissen |
| 2021 | ITC | Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions. | Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui |
| 2020 | DATE | Impact of Magnetic Coupling and Density on STT-MRAM Performance. | Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui |
| 2020 | ETS | Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults. | Min-Chun Hu, Zhan Gao, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Cheng-Wen Wu, Erik Jan Marinissen |
| 2020 | ETS | Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios. | Michele Stucchi, Ferenc Fodor, Erik Jan Marinissen |
| 2020 | ITC | Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs. | Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui |
| 2019 | ETS | Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing. | Lizhou Wu, Siddharth Rao, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Erik Jan Marinissen, Farrukh Yasin, Sebastien Couet, Said Hamdioui, Gouri Sankar Kar |
| 2019 | ITC | Device-Aware Test: A New Test Approach Towards DPPB Level. | Moritz Fieback, Lizhou Wu, Guilherme Cardoso Medeiros, Hassen Aziza, Siddharth Rao, Erik Jan Marinissen, Mottaqiallah Taouil, Said Hamdioui |
| 2019 | ITC | Application of Cell-Aware Test on an Advanced 3nm CMOS Technology Library. | Zhan Gao, Santosh Malagi, Min-Chun Hu, Joe Swenton, Rogier Baert, Jos Huisken, Bilal Chehab, Kees Goossens, Erik Jan Marinissen |
| 2018 | ETS | IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers. | Yu Li, Ming Shao, Hailong Jiao, Adam Cron, Sandeep Bhatia, Erik Jan Marinissen |
| 2018 | ETS | Automatic generation of in-circuit tests for board assembly defects. | Harm van Schaaijk, Martien Spierings, Erik Jan Marinissen |
| 2018 | ITC | On-Chip Toggle Generators to Provide Realistic Conditions during Test of Digital 2D-SoCs and 3D-SICs. | Leonidas Katselas, Alkis A. Hatzopoulos, Hailong Jiao, Christos Papameletis, Erik Jan Marinissen |
| 2018 | ITC | Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. | Erik Jan Marinissen, Ferenc Fodor, Arnita Podpod, Michele Stucchi, Yu-Rong Jian, Cheng-Wen Wu |
| 2018 | ITC | Electrical Modeling of STT-MRAM Defects. | Lizhou Wu, Mottaqiallah Taouil, Siddharth Rao, Erik Jan Marinissen, Said Hamdioui |
| 2016 | ETS | Test-station for flexible semi-automatic wafer-level silicon photonics testing. | Jeroen De Coster, Peter De Heyn, Marianna Pantouvaki, Brad Snyder, Hongtao Chen, Erik Jan Marinissen, Philippe Absil, Joris Van Campenhout, Bryan Bolt |
| 2016 | ETS | IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs. | Erik Jan Marinissen, Teresa L. McLaurin, Hailong Jiao |
| 2016 | ETS | IoT: Source of test challenges. | Erik Jan Marinissen, Yervant Zorian, Mario Konijnenburg, Chih-Tsun Huang, Ping-Hsuan Hsieh, Peter Cockburn, Jeroen Delvaux, Vladimir Rozic, Bohan Yang, Dave Singele, Ingrid Verbauwhede, Cedric Mayor, Robert Van Rijsinge, Cocoy Reyes |
| 2015 | ITC | Automated testing of bare die-to-die stacks. | Erik Jan Marinissen, Bart De Wachter, Teng Wang, Jens Fiedler, Jorg Kiesewetter, Karsten Stoll |
| 2014 | DATE | Interconnect test for 3D stacked memory-on-logic. | Mottaqiallah Taouil, Mahmoud Masadeh, Said Hamdioui, Erik Jan Marinissen |
| 2014 | ITC | Vesuvius-3D: A 3D-DfT demonstrator. | Erik Jan Marinissen, Bart De Wachter, Stephen O'Loughlin, Sergej Deutsch, Christos Papameletis, Tobias Burgherr |
| 2014 | ITC | Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface. | Erik Jan Marinissen, Bart De Wachter, Ken Smith, Jorg Kiesewetter, Mottaqiallah Taouil, Said Hamdioui |
| 2014 | VTS | Quality versus cost analysis for 3D Stacked ICs. | Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen |
| 2013 | ASPDAC | Design issues in heterogeneous 3D/2.5D integration. | Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne |
| 2013 | DDECS | Creating options for 3D-SIC testing. | Erik Jan Marinissen |
| 2013 | ETS | Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers. | Christos Papameletis, Brion L. Keller, Vivek Chickermane, Erik Jan Marinissen, Said Hamdioui |
| 2013 | ITC | Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs. | Sergej Deutsch, Krishnendu Chakrabarty, Erik Jan Marinissen |
| 2012 | DATE | Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs. | Erik Jan Marinissen |
| 2012 | DATE | EDA solutions to new-defect detection in advanced process technologies. | Erik Jan Marinissen, Gilbert Vandling, Sandeep Kumar Goel, Friedrich Hapke, Jason Rivers, Nikolaus Mittermaier, Swapnil Bahl |
| 2012 | ITC | DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. | Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen |
| 2011 | ETS | DfT Architecture for 3D-SICs with Multiple Towers. | Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu |
| 2011 | ITC | Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. | Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu |
| 2011 | ITC | Evaluation of TSV and micro-bump probing for wide I/O testing. | Ken Smith, Peter Hanaway, Mike Jolley, Reed Gleason, Eric Strid, Tom Daenen, Luc Dupas, Bruno Knuts, Erik Jan Marinissen, Marc Van Dievel |
| 2010 | DATE | Testing TSV-based three-dimensional stacked ICs. | Erik Jan Marinissen |
| 2010 | DATE | Adapting to adaptive testing. | Erik Jan Marinissen, Adit D. Singh, Dan Glotter, Marco Esposito, John M. Carulli Jr., Amit Nahar, Kenneth M. Butler, Davide Appello, Chris Portelli |
| 2010 | ETS | Test-architecture optimization for TSV-based 3D stacked ICs. | Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree |
| 2010 | ETS | On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. | Jouke Verbree, Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis |
| 2010 | IOLTS | 3D integration: Circuit design, test, and reliability challenges. | Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal |
| 2010 | ITC | Optimization methods for post-bond die-internal/external testing in 3D stacked ICs. | Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen |
| 2010 | ITC | On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs. | Mottaqiallah Taouil, Said Hamdioui, Jouke Verbree, Erik Jan Marinissen |
| 2010 | VTS | A structured and scalable test access architecture for TSV-based 3D stacked ICs. | Erik Jan Marinissen, Jouke Verbree, Mario Konijnenburg |
| 2009 | DATE | Contactless testing: Possibility or pipe-dream? | Erik Jan Marinissen, Dae Young Lee, John P. Hayes, Chris Sellathamby, Brian Moore, Steven Slupsky, Laurence Pujol |
| 2009 | ITC | Testing 3D chips containing through-silicon vias. | Erik Jan Marinissen, Yervant Zorian |
| 2008 | DATE | Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing. | Ozgur Sinanoglu, Erik Jan Marinissen |
| 2008 | ETS | Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism. | Ardy van den Berg, Pengwei Ren, Erik Jan Marinissen, Georgi Gaydadjiev, Kees Goossens |
| 2007 | DATE | Test quality analysis and improvement for an embedded asynchronous FIFO. | Tobias Dubois, Erik Jan Marinissen, Mohamed Azimane, Paul Wielage, Erik Larsson, Clemens Wouters |
| 2007 | DATE | Design and DfT of a high-speed area-efficient embedded asynchronous FIFO. | Paul Wielage, Erik Jan Marinissen, Michel Altheimer, Clemens Wouters |
| 2007 | ITC | Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects. | Jeroen Geuzebroek, Erik Jan Marinissen, Ananta K. Majhi, Andreas Glowatz, Friedrich Hapke |
| 2006 | DATE | Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. | Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty |
| 2006 | ETS | Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism. | Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes |
| 2005 | DATE | On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2005 | DATE | Challenges in Embedded Memory Design and Test. | Erik Jan Marinissen, Betty Prince, Doris Keitel-Schulz, Yervant Zorian |
| 2005 | ETS | Test scheduling for modular SOCs in an abort-on-fail environment. | Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen |
| 2004 | DATE | Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip. | Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk |
| 2004 | ETS | User-constrained test architecture design for modular SOC testing. | Ludovic A. Krundel, Sandeep Kumar Goel, Erik Jan Marinissen, Marie-Lise Flottes, Bruno Rouzeyre |
| 2004 | ITC | Security vs. Test Quality: Can We Really Only Have One at a Time? | Erik Jan Marinissen |
| 2004 | ITC | IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. | Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty |
| 2004 | ITC | Trends in Testing Integrated Circuits. | Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge |
| 2003 | DATE | Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2003 | DATE | Creating Value Through Test. | Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Mller |
| 2003 | ETS | Control-aware test architecture design for modular SOC testing. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2003 | ETS | Yield analysis for repairable embedded memories. | Anuja Sehgal, Aishwarya Dubey, Erik Jan Marinissen, Clemens Wouters, Harald P. E. Vranken, Krishnendu Chakrabarty |
| 2003 | ITC | Optimal Interconnect ATPG Under a Ground-Bounce Constraint. | Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen |
| 2002 | DAC | Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen |
| 2002 | DATE | Efficient Wrapper/TAM Co-Optimization for Large SOCs. | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen |
| 2002 | ETS | A novel test time reduction algorithm for test architecture design for core-based system chips. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2002 | ITC | Effective and Efficient Test Architecture Design for SOCs. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2002 | ITC | Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. | Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty |
| 2002 | ITC | A Set of Benchmarks fo Modular Testing of SOCs. | Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty |
| 2002 | VTS | Cluster-Based Test Architecture Design for System-on-Chip. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2002 | VTS | On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen |
| 2001 | ITC | Test wrapper and test access mechanism co-optimization for system-on-chip. | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen |
| 2000 | DAC | System chip test: how will it impact your design? | Yervant Zorian, Erik Jan Marinissen |
| 2000 | ITC | Application of deterministic logic BIST on industrial circuits. | Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen |
| 2000 | ITC | On using IEEE P1500 SECT for test plug-n-play. | Yervant Zorian, Erik Jan Marinissen, Rohit Kapur |
| 2000 | ITC | Wrapper design for embedded core test. | Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel |
| 1999 | ETS | The role of test protocols in testing embedded-core-based system ICs. | Erik Jan Marinissen, Maurice Lousberg |
| 1999 | ITC | Towards a standard for embedded core test: an example. | Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel |
| 1998 | ITC | Scan chain design for test time reduction in core-based ICs. | Joep Aerts, Erik Jan Marinissen |
| 1998 | ITC | A structured and scalable mechanism for test access to embedded reusable cores. | Erik Jan Marinissen, Robert G. J. Arendsen, Gerard Bos, Hans Dingemanse, Maurice Lousberg, Clemens Wouters |
| 1998 | ITC | Testing embedded-core based system chips. | Yervant Zorian, Erik Jan Marinissen, Sujit Dey |