Vivek Chickermane
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
30
Venues
7
Active years
1990–2025
Best venue rank
A*
Where they publish
Papers
30 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ITC | Embedded Trace: A Key Enabler for Silicon Lifecycle Management. | Vivek Chickermane, Marcel Zak, Mat O'Donnell |
| 2025 | ITC | Embedded Trace: A Key Enabler for Silicon Lifecycle Management. | Vivek Chickermane, Marcel Zak, Mat O'Donnell |
| 2022 | ITC | PPA Optimization of Test Points in Automotive Designs. | Brian Foutz, Sarthak Singhal, Prateek Kumar Rai, Krishna Chakravadhanula, Vivek Chickermane, Bharath Nandakumar, Sameer Chillarige, Christos Papameletis, Satish Ravichandran |
| 2019 | ITC | Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications. | Christos Papameletis, Vivek Chickermane, Brian Foutz, Sarthak Singhal, Krishna Chakravadhanula |
| 2019 | VTS | Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults. | Irith Pomeranz, Vivek Chickermane, Srikanth Venkataraman |
| 2017 | ITC | Advancing test compression to the physical dimension. | Krishna Chakravadhanula, Vivek Chickermane, Paul Cunningham, Brian Foutz, Dale Meehl, Louis Milano, Christos Papameletis, David Scott, Steev Wilcox |
| 2014 | ITC | Efficient testing of hierarchical core-based SOCs. | Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen |
| 2014 | VLSID | Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices. | Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula |
| 2014 | VTS | Innovative practices session 1C: Existing/emerging low power techniques. | Charutosh Dixit, Ramesh C. Tekumalla, Wei Zhao, Nilanjan Mukherjee, Vivek Chickermane |
| 2013 | ETS | Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers. | Christos Papameletis, Brion L. Keller, Vivek Chickermane, Erik Jan Marinissen, Said Hamdioui |
| 2013 | ITC | SmartScan - Hierarchical test compression for pin-limited low power designs. | Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Akhil Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj |
| 2013 | ITC | Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. | Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim |
| 2012 | ITC | DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. | Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen |
| 2010 | ITC | Low cost at-speed testing using On-Product Clock Generation compatible with test compression. | Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise |
| 2009 | ITC | Capture power reduction using clock gating aware test generation. | Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang |
| 2008 | ITC | A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. | Vivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula |
| 2004 | ITC | Channel Masking Synthesis for Efficient On-Chip Test Compression. | Vivek Chickermane, Brian Foutz, Brion L. Keller |
| 2004 | ITC | An Economic Analysis and ROI Model for Nanometer Test. | Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane |
| 2001 | ITC | A building block BIST methodology for SOC designs: a case study. | Patrick R. Gallagher Jr., Vivek Chickermane, Steven Gregor, Thomas S. Pierre |
| 2000 | VTS | Integrating Logic BIST in VLSI Designs with Embedded Memories. | Vivek Chickermane, Scott Richter, Carl Barnhart |
| 1997 | ITC | Addressing Early Design-For-Test Synthesis in a Production Environment. | Vivek Chickermane, Kamran Zarrineh |
| 1996 | ICCD | A Design For Test Perspective on I/O Management. | Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer |
| 1993 | DAC | Non-Scan Design-for-Testability Techniques for Sequential Circuits. | Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel |
| 1993 | VTS | Impact of high level functional constraints on testability. | Jaushin Lee, Vivek Chickermane, Janak H. Patel |
| 1992 | DAC | APT: An Area-Performance-Testability Driven Placement Algorithm. | Sungho Kim, Prithviraj Banerjee, Vivek Chickermane, Janak H. Patel |
| 1992 | ICCAD | A comparative study of design for testability methods using high-level and gate-level descriptions. | Vivek Chickermane, Jaushin Lee, Janak H. Patel |
| 1992 | ITC | Design for Testability Using Architectural Descriptions. | Vivek Chickermane, Jaushin Lee, Janak H. Patel |
| 1992 | VTS | Probe point insertion for at-speed test. | Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel |
| 1991 | ICCAD | A Fault Oriented Partial Scan Design Approach. | Vivek Chickermane, Janak H. Patel |
| 1990 | ITC | An optimization based approach to the partial scan design problem. | Vivek Chickermane, Janak H. Patel |