Sandeep Kumar Goel
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
41
Venues
6
Active years
2000–2026
Best venue rank
A*
Where they publish
Papers
41 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ETS | Shaping the Future of Multi-Die Stacking: Overcoming Challenges through Collaboration and Standards. | Sandeep Kumar Goel |
| 2025 | ITC | Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging | Partho Bhoumik, Arjun Chaudhuri, Sandeep Kumar Goel, Krishnendu Chakrabarty |
| 2025 | ITC | Leveraging UCIe Interface for Silicon Health & Reliabiilty of Chiplets in a 3D Stack. | Sandeep Kumar Goel, Ankita Patidar, Stanley John, Frank Lee, Min-Jer Wang, Daniel F. J. Yang, Yervant Zorian, Manish Arora, Firooz Massoudi, Shaan Awasthi, Stelios Balalis, Velmurugan Pathervellaichamy, Bharath Shankaranarayanan, Narasimhalu Raju, Gurgen Harutyunyan, Grigor Tshagharyan, Vahagn Hovakimyan, Arman Karagyozyan, Alvina Manucharyan |
| 2025 | ITC | Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost. | Sandeep Kumar Goel, Ankita Patidar, Yue Tian, Frank Lee |
| 2025 | ITC | A Novel Omnidirectional 3D Test Access Architecture for Advanced System-on-Wafer (SoW) Applications. | Hiroyuki Iwata, Sandeep Kumar Goel, Ankita Patidar, Fumiaki Takashima, Frank Lee |
| 2024 | ETS | Scan Design Using Unsupervised Machine Learning to Reduce Functional Timing and Area Impact. | Sandeep Kumar Goel, Ankita Patidar, Frank Lee |
| 2024 | ITC | Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests. | Sandeep Kumar Goel, Moiz Khan, Ankita Patidar, Frank Lee, Vuong Nguyen, Bharath Shankaranarayanan, Doo Kim, Manish Arora |
| 2024 | ITC | Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard. | Sandeep Kumar Goel, Ankita Patidar, Moiz Khan, Frank Lee, Anshuman Chandra, Martin Keim, Naim Lemar, Jonathan Gaudet, Quoc Phan, Vidya Neerkundar |
| 2023 | ITC | A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation. | Anshuman Chandra, Moiz Khan, Ankita Patidar, Fumiaki Takashima, Sandeep Kumar Goel, Bharath Shankaranarayanan, Vuong Nguyen, Vistrita Tyagi, Manish Arora |
| 2022 | VTS | Innovative Practices Track: Test of 3D ICs & Chiplets. | Sandeep Kumar Goel, Sandeep Pendharkar, Chunsheng Liu |
| 2015 | ITC | Efficient observation-point insertion for diagnosability enhancement in digital circuits. | Zipeng Li, Sandeep Kumar Goel, Frank Lee, Krishnendu Chakrabarty |
| 2013 | ITC | Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. | Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim |
| 2012 | DATE | EDA solutions to new-defect detection in advanced process technologies. | Erik Jan Marinissen, Gilbert Vandling, Sandeep Kumar Goel, Friedrich Hapke, Jason Rivers, Nikolaus Mittermaier, Swapnil Bahl |
| 2012 | ICCAD | Test challenges in designing complex 3D chips: What in on the horizon for EDA industry?: Designer track. | Sandeep Kumar Goel |
| 2012 | ITC | DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. | Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen |
| 2011 | ETS | DfT Architecture for 3D-SICs with Multiple Towers. | Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu |
| 2011 | ITC | Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. | Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu |
| 2010 | ETS | Test-architecture optimization for TSV-based 3D stacked ICs. | Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree |
| 2009 | ITC | Accurate measurement of small delay defect coverage of test patterns. | Narendra Devta-Prasanna, Sandeep Kumar Goel, Arun Gunda, Mark Ward, P. Krishnamurthy |
| 2009 | ITC | Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study. | Sandeep Kumar Goel, Narendra Devta-Prasanna, Mark Ward |
| 2009 | VTS | Effective and Efficient Test Pattern Generation for Small Delay Defect. | Sandeep Kumar Goel, Narendra Devta-Prasanna, Ritesh P. Turakhia |
| 2009 | VTS | Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study. | Ritesh P. Turakhia, Mark Ward, Sandeep Kumar Goel, Brady Benware |
| 2006 | DAC | Fault detection and diagnosis with parity trees for space compaction of test responses. | Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jrgen Schlffel, Friedrich Hapke |
| 2006 | DATE | Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. | Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty |
| 2006 | ETS | Testing and Diagnosis of Power Switches in SOCs. | Sandeep Kumar Goel, Maurice Meijer, Jos Pineda de Gyvez |
| 2005 | DATE | On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2005 | ETS | Test scheduling for modular SOCs in an abort-on-fail environment. | Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen |
| 2004 | DAC | Automatic generation of breakpoint hardware for silicon debug. | Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel |
| 2004 | DATE | Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip. | Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk |
| 2004 | ETS | User-constrained test architecture design for modular SOC testing. | Ludovic A. Krundel, Sandeep Kumar Goel, Erik Jan Marinissen, Marie-Lise Flottes, Bruno Rouzeyre |
| 2004 | ITC | IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. | Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty |
| 2003 | DATE | Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2003 | ETS | Control-aware test architecture design for modular SOC testing. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2002 | ETS | A novel test time reduction algorithm for test architecture design for core-based system chips. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2002 | ETS | Data invalidation analysis for scan-based debug on multiple-clock system chips. | Sandeep Kumar Goel, Bart Vermeulen |
| 2002 | ITC | Effective and Efficient Test Architecture Design for SOCs. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2002 | ITC | Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. | Sandeep Kumar Goel, Bart Vermeulen |
| 2002 | ITC | Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. | Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty |
| 2002 | ITC | Core-Based Scan Architecture for Silicon Debug. | Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel |
| 2002 | VTS | Cluster-Based Test Architecture Design for System-on-Chip. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2000 | ITC | Wrapper design for embedded core test. | Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel |